Merge remote-tracking branches 'spi/topic/dw', 'spi/topic/flash-read', 'spi/topic/fsl-dspi', 'spi/topic/fsl-espi' and 'spi/topic/kconfig' into spi-next
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c36581c9a5
@ -13,8 +13,7 @@ Required properties:
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Optional property:
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- big-endian: If present the dspi device's registers are implemented
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in big endian mode, otherwise in native mode(same with CPU), for more
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detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.
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in big endian mode.
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Optional SPI slave node properties:
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- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
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@ -410,7 +410,6 @@ config SPI_OMAP_UWIRE
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config SPI_OMAP24XX
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tristate "McSPI driver for OMAP"
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depends on HAS_DMA
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depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH
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depends on ARCH_OMAP2PLUS || COMPILE_TEST
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help
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SPI master controller for OMAP24XX and later Multichannel SPI
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@ -469,7 +468,6 @@ config SPI_PXA2XX_PCI
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config SPI_ROCKCHIP
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tristate "Rockchip SPI controller driver"
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depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH
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help
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This selects a driver for Rockchip SPI controller.
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@ -67,7 +67,7 @@ static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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dws->irq = pdev->irq;
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/*
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* Specific handling for paltforms, like dma setup,
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* Specific handling for platforms, like dma setup,
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* clock rate, FIFO depth.
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*/
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if (desc) {
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@ -121,18 +121,22 @@ enum dspi_trans_mode {
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struct fsl_dspi_devtype_data {
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enum dspi_trans_mode trans_mode;
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u8 max_clock_factor;
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};
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static const struct fsl_dspi_devtype_data vf610_data = {
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.trans_mode = DSPI_EOQ_MODE,
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.max_clock_factor = 2,
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};
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static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
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.trans_mode = DSPI_TCFQ_MODE,
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.max_clock_factor = 8,
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};
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static const struct fsl_dspi_devtype_data ls2085a_data = {
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.trans_mode = DSPI_TCFQ_MODE,
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.max_clock_factor = 8,
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};
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struct fsl_dspi {
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@ -726,6 +730,9 @@ static int dspi_probe(struct platform_device *pdev)
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}
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clk_prepare_enable(dspi->clk);
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master->max_speed_hz =
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clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
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init_waitqueue_head(&dspi->waitq);
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platform_set_drvdata(pdev, master);
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@ -245,7 +245,12 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
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if (ret)
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return ret;
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wait_for_completion(&mpc8xxx_spi->done);
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/* Won't hang up forever, SPI bus sometimes got lost interrupts... */
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ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ);
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if (ret == 0)
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dev_err(mpc8xxx_spi->dev,
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"Transaction hanging up (left %d bytes)\n",
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mpc8xxx_spi->count);
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/* disable rx ints */
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mpc8xxx_spi_write_reg(®_base->mask, 0);
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@ -539,16 +544,31 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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if (events & SPIE_NE) {
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u32 rx_data, tmp;
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u8 rx_data_8;
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int rx_nr_bytes = 4;
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int ret;
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/* Spin until RX is done */
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while (SPIE_RXCNT(events) < min(4, mspi->len)) {
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cpu_relax();
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events = mpc8xxx_spi_read_reg(®_base->event);
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if (SPIE_RXCNT(events) < min(4, mspi->len)) {
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ret = spin_event_timeout(
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!(SPIE_RXCNT(events =
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mpc8xxx_spi_read_reg(®_base->event)) <
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min(4, mspi->len)),
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10000, 0); /* 10 msec */
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if (!ret)
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dev_err(mspi->dev,
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"tired waiting for SPIE_RXCNT\n");
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}
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if (mspi->len >= 4) {
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rx_data = mpc8xxx_spi_read_reg(®_base->receive);
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} else if (mspi->len <= 0) {
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dev_err(mspi->dev,
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"unexpected RX(SPIE_NE) interrupt occurred,\n"
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"(local rxlen %d bytes, reg rxlen %d bytes)\n",
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min(4, mspi->len), SPIE_RXCNT(events));
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rx_nr_bytes = 0;
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} else {
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rx_nr_bytes = mspi->len;
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tmp = mspi->len;
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rx_data = 0;
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while (tmp--) {
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@ -559,7 +579,7 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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rx_data <<= (4 - mspi->len) * 8;
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}
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mspi->len -= 4;
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mspi->len -= rx_nr_bytes;
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if (mspi->rx)
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mspi->get_rx(rx_data, mspi);
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@ -372,6 +372,7 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
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* @unprepare_message: undo any work done by prepare_message().
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* @spi_flash_read: to support spi-controller hardwares that provide
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* accelerated interface to read from flash devices.
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* @flash_read_supported: spi device supports flash read
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* @cs_gpios: Array of GPIOs to use as chip select lines; one per CS
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* number. Any individual value may be -ENOENT for CS lines that
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* are not GPIOs (driven by the SPI controller itself).
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@ -529,6 +530,7 @@ struct spi_master {
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struct spi_message *message);
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int (*spi_flash_read)(struct spi_device *spi,
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struct spi_flash_read_message *msg);
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bool (*flash_read_supported)(struct spi_device *spi);
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/*
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* These hooks are for drivers that use a generic implementation
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@ -1158,7 +1160,9 @@ struct spi_flash_read_message {
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/* SPI core interface for flash read support */
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static inline bool spi_flash_read_supported(struct spi_device *spi)
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{
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return spi->master->spi_flash_read ? true : false;
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return spi->master->spi_flash_read &&
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(!spi->master->flash_read_supported ||
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spi->master->flash_read_supported(spi));
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}
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int spi_flash_read(struct spi_device *spi,
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