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[MIPS] Fix IP32 breakage

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- suppress master aborts during config read
- set io_map_base
- only fixup end of iomem resource to avoid failing request_resource
  in serial driver
- killed useless setting of crime_int bit, which caused wrong interrupts
- use physcial address for serial port platform device and let 8250
  driver do the ioremap

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thomas Bogendoerfer 2008-01-05 12:13:11 +01:00 committed by Ralf Baechle
parent 9cfacb790f
commit c990081bf8
4 changed files with 19 additions and 13 deletions
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7
arch/mips/pci/ops-mace.c
View File

@ -42,6 +42,10 @@ static int
mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 *val)
{
u32 control = mace->pci.control;
/* disable master aborts interrupts during config read */
mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
mace->pci.config_addr = mkaddr(bus, devfn, reg);
switch (size) {
case 1:
@ -54,6 +58,9 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
*val = mace->pci.config_data.l;
break;
}
/* ack possible master abort */
mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
mace->pci.control = control;
DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);

4
arch/mips/pci/pci-ip32.c
View File

@ -119,6 +119,7 @@ static struct pci_controller mace_pci_controller = {
.iommu = 0,
.mem_offset = MACE_PCI_MEM_OFFSET,
.io_offset = 0,
.io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),
};
static int __init mace_init(void)
@ -135,7 +136,8 @@ static int __init mace_init(void)
BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
"MACE PCI error", NULL));
iomem_resource = mace_pci_mem_resource;
/* extend memory resources */
iomem_resource.end = mace_pci_mem_resource.end;
ioport_resource = mace_pci_io_resource;
register_pci_controller(&mace_pci_controller);

1
arch/mips/sgi-ip32/ip32-irq.c
View File

@ -426,7 +426,6 @@ static void ip32_irq0(void)
crime_int = crime->istat & crime_mask;
irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
crime_int = 1 << irq;
if (crime_int & CRIME_MACEISA_INT_MASK) {
unsigned long mace_int = mace->perif.ctrl.istat;

20
arch/mips/sgi-ip32/ip32-platform.c
View File

@ -13,21 +13,22 @@
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>
/*
* .iobase isn't a constant (in the sense of C) so we fill it in at runtime.
*/
#define MACE_PORT(int) \
#define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1)
#define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2)
#define MACE_PORT(offset,_irq) \
{ \
.irq = int, \
.mapbase = MACE_BASE + offset, \
.irq = _irq, \
.uartclk = 1843200, \
.iotype = UPIO_MEM, \
.flags = UPF_SKIP_TEST, \
.flags = UPF_SKIP_TEST|UPF_IOREMAP, \
.regshift = 8, \
}
static struct plat_serial8250_port uart8250_data[] = {
MACE_PORT(MACEISA_SERIAL1_IRQ),
MACE_PORT(MACEISA_SERIAL2_IRQ),
MACE_PORT(MACEISA_SERIAL1_OFFS, MACEISA_SERIAL1_IRQ),
MACE_PORT(MACEISA_SERIAL2_OFFS, MACEISA_SERIAL2_IRQ),
{ },
};
@ -41,9 +42,6 @@ static struct platform_device uart8250_device = {
static int __init uart8250_init(void)
{
uart8250_data[0].membase = (void __iomem *) &mace->isa.serial1;
uart8250_data[1].membase = (void __iomem *) &mace->isa.serial2;
return platform_device_register(&uart8250_device);
}