ASoC: tlv320aic3x: Fix codec pll configure bug
In sound/soc/codecs/tlv320aic3x.c data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); snd_soc_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT)); In the above code, pll-p value is OR'ed with previous value without clearing it. Bug is not seen if pll-p value doesn't change across Sampling frequency. However on some platforms (like AM335x EVM-SK), pll-p may have different values across different sampling frequencies. In such case, above code configures the pll with a wrong value. Because of this bug, when a audio stream is played with pll value different from previous stream, audio is heard as differently(like its stretched). Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: stable@vger.kernel.org
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@ -935,9 +935,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
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}
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found:
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data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
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snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
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data | (pll_p << PLLP_SHIFT));
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snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
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snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
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pll_r << PLLR_SHIFT);
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snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
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@ -166,6 +166,7 @@
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/* PLL registers bitfields */
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#define PLLP_SHIFT 0
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#define PLLP_MASK 7
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#define PLLQ_SHIFT 3
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#define PLLR_SHIFT 0
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#define PLLJ_SHIFT 2
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