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Merge branch 'next/cleanup-s3c24xx-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup

Browse Source 
From Kukjin Kim:
This is 4th cleanup for Samsung S3C24XX stuff, and removes plat-s3c24xx
directory.

* 'next/cleanup-s3c24xx-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: S3C24XX: header mach/regs-mem.h local
  ARM: S3C24XX: header mach/regs-power.h local
  ARM: S3C24XX: header mach/regs-s3c2412-mem.h local
  ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/
This commit is contained in:
Olof Johansson 2013-02-05 17:01:56 -08:00
commit cf55f672c3
41 changed files with 266 additions and 478 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
View File

@ -1079,7 +1079,6 @@ source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-sa1100/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"

2
arch/arm/Makefile
View File

@ -204,7 +204,7 @@ plat-$(CONFIG_ARCH_S3C64XX) += samsung
plat-$(CONFIG_PLAT_IOP) += iop
plat-$(CONFIG_PLAT_ORION) += orion
plat-$(CONFIG_PLAT_PXA) += pxa
plat-$(CONFIG_PLAT_S3C24XX) += s3c24xx samsung
plat-$(CONFIG_PLAT_S3C24XX) += samsung
plat-$(CONFIG_PLAT_S5P) += samsung
plat-$(CONFIG_PLAT_SPEAR) += spear
plat-$(CONFIG_PLAT_VERSATILE) += versatile

104
arch/arm/mach-s3c24xx/Kconfig
View File

@ -9,6 +9,15 @@
if ARCH_S3C24XX
config PLAT_S3C24XX
def_bool y
select ARCH_REQUIRE_GPIOLIB
select NO_IOPORT
select S3C_DEV_NAND
select IRQ_DOMAIN
help
Base platform code for any Samsung S3C24XX device
menu "SAMSUNG S3C24XX SoCs Support"
comment "S3C24XX SoCs"
@ -83,6 +92,17 @@ config CPU_S3C2443
# common code
config S3C2410_CLOCK
bool
help
Clock code for the S3C2410, and similar processors which
is currently includes the S3C2410, S3C2440, S3C2442.
config S3C24XX_DCLK
bool
help
Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
config S3C24XX_SMDK
bool
help
@ -111,6 +131,22 @@ config S3C24XX_SETUP_TS
help
Compile in platform device definition for Samsung TouchScreen.
config S3C24XX_DMA
bool "S3C2410 DMA support"
depends on ARCH_S3C24XX
select S3C_DMA
help
S3C2410 DMA support. This is needed for drivers like sound which
use the S3C2410's DMA system to move data to and from the
peripheral blocks.
config S3C2410_DMA_DEBUG
bool "S3C2410 DMA support debug"
depends on ARCH_S3C24XX && S3C2410_DMA
help
Enable debugging output for the DMA code. This option sends info
to the kernel log, at priority KERN_DEBUG.
config S3C2410_DMA
bool
depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@ -123,6 +159,74 @@ config S3C2410_PM
help
Power Management code common to S3C2410 and better
# low-level serial option nodes
config CPU_LLSERIAL_S3C2410_ONLY
bool
default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
config CPU_LLSERIAL_S3C2440_ONLY
bool
default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
config CPU_LLSERIAL_S3C2410
bool
help
Selected if there is an S3C2410 (or register compatible) serial
low-level implementation needed
config CPU_LLSERIAL_S3C2440
bool
help
Selected if there is an S3C2440 (or register compatible) serial
low-level implementation needed
# gpio configurations
config S3C24XX_GPIO_EXTRA
int
default 128 if S3C24XX_GPIO_EXTRA128
default 64 if S3C24XX_GPIO_EXTRA64
default 16 if ARCH_H1940
default 0
config S3C24XX_GPIO_EXTRA64
bool
help
Add an extra 64 gpio numbers to the available GPIO pool. This is
available for boards that need extra gpios for external devices.
config S3C24XX_GPIO_EXTRA128
bool
help
Add an extra 128 gpio numbers to the available GPIO pool. This is
available for boards that need extra gpios for external devices.
# cpu frequency items common between s3c2410 and s3c2440/s3c2442
config S3C2410_IOTIMING
bool
depends on CPU_FREQ_S3C24XX
help
Internal node to select io timing code that is common to the s3c2410
and s3c2440/s3c2442 cpu frequency support.
config S3C2410_CPUFREQ_UTILS
bool
depends on CPU_FREQ_S3C24XX
help
Internal node to select timing code that is common to the s3c2410
and s3c2440/s3c244 cpu frequency support.
# cpu frequency support common to s3c2412, s3c2413 and s3c2442
config S3C2412_IOTIMING
bool
depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
help
Intel node to select io timing code that is common to the s3c2412
and the s3c2443.
# cpu-specific sections
if CPU_S3C2410

14
arch/arm/mach-s3c24xx/Makefile
View File

@ -14,7 +14,7 @@ obj- :=
# core
obj-y += common.o
obj-y += common.o irq.o
obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o
@ -47,9 +47,21 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
# common code
obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
obj-$(CONFIG_S3C24XX_DMA) += dma.o
obj-$(CONFIG_S3C2410_CLOCK) += clock-s3c2410.o
obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o
obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o
obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpufreq.o
obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o
#
# machine support
# following is ordered alphabetically by option text.

3
arch/arm/plat-s3c24xx/clock-dclk.c → arch/arm/mach-s3c24xx/clock-dclk.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s3c24xx/clock-dclk.c
*
/*
* Copyright (c) 2004-2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/

3
arch/arm/plat-s3c24xx/s3c2410-clock.c → arch/arm/mach-s3c24xx/clock-s3c2410.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-s3c2410/clock.c
*
/*
* Copyright (c) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*

3
arch/arm/plat-s3c24xx/cpu-freq-debugfs.c → arch/arm/mach-s3c24xx/cpufreq-debugfs.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
*
/*
* Copyright (c) 2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>

3
arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
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@ -25,12 +25,13 @@
#include <asm/mach/map.h>
#include <mach/regs-clock.h>
#include <mach/regs-s3c2412-mem.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/cpu-freq-core.h>
#include "s3c2412.h"
/* our clock resources. */
static struct clk *xtal;
static struct clk *fclk;

6
arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c → arch/arm/mach-s3c24xx/cpufreq-utils.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
*
/*
* Copyright (c) 2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
@ -17,11 +16,12 @@
#include <linux/io.h>
#include <mach/map.h>
#include <mach/regs-mem.h>
#include <mach/regs-clock.h>
#include <plat/cpu-freq-core.h>
#include "regs-mem.h"
/**
* s3c2410_cpufreq_setrefresh - set SDRAM refresh value
* @cfg: The frequency configuration

3
arch/arm/plat-s3c24xx/cpu-freq.c → arch/arm/mach-s3c24xx/cpufreq.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s3c24xx/cpu-freq.c
*
/*
* Copyright (c) 2006-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>

1
arch/arm/mach-s3c24xx/dma-s3c2410.c
View File

@ -27,7 +27,6 @@
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <plat/regs-iis.h>

1
arch/arm/mach-s3c24xx/dma-s3c2412.c
View File

@ -27,7 +27,6 @@
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <plat/regs-iis.h>

1
arch/arm/mach-s3c24xx/dma-s3c2440.c
View File

@ -27,7 +27,6 @@
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <plat/regs-iis.h>

1
arch/arm/mach-s3c24xx/dma-s3c2443.c
View File

@ -27,7 +27,6 @@
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <plat/regs-iis.h>

3
arch/arm/plat-s3c24xx/dma.c → arch/arm/mach-s3c24xx/dma.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s3c24xx/dma.c
*
/*
* Copyright 2003-2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*

202
arch/arm/mach-s3c24xx/include/mach/regs-mem.h
View File

@ -1,202 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/regs-mem.h
*
* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 Memory Control register definitions
*/
#ifndef __ASM_ARM_MEMREGS_H
#define __ASM_ARM_MEMREGS_H
#ifndef S3C2410_MEMREG
#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#endif
/* bus width, and wait state control */
#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
/* bank zero config - note, pinstrapped from OM pins! */
#define S3C2410_BWSCON_DW0_16 (1<<1)
#define S3C2410_BWSCON_DW0_32 (2<<1)
/* bank one configs */
#define S3C2410_BWSCON_DW1_8 (0<<4)
#define S3C2410_BWSCON_DW1_16 (1<<4)
#define S3C2410_BWSCON_DW1_32 (2<<4)
#define S3C2410_BWSCON_WS1 (1<<6)
#define S3C2410_BWSCON_ST1 (1<<7)
/* bank 2 configurations */
#define S3C2410_BWSCON_DW2_8 (0<<8)
#define S3C2410_BWSCON_DW2_16 (1<<8)
#define S3C2410_BWSCON_DW2_32 (2<<8)
#define S3C2410_BWSCON_WS2 (1<<10)
#define S3C2410_BWSCON_ST2 (1<<11)
/* bank 3 configurations */
#define S3C2410_BWSCON_DW3_8 (0<<12)
#define S3C2410_BWSCON_DW3_16 (1<<12)
#define S3C2410_BWSCON_DW3_32 (2<<12)
#define S3C2410_BWSCON_WS3 (1<<14)
#define S3C2410_BWSCON_ST3 (1<<15)
/* bank 4 configurations */
#define S3C2410_BWSCON_DW4_8 (0<<16)
#define S3C2410_BWSCON_DW4_16 (1<<16)
#define S3C2410_BWSCON_DW4_32 (2<<16)
#define S3C2410_BWSCON_WS4 (1<<18)
#define S3C2410_BWSCON_ST4 (1<<19)
/* bank 5 configurations */
#define S3C2410_BWSCON_DW5_8 (0<<20)
#define S3C2410_BWSCON_DW5_16 (1<<20)
#define S3C2410_BWSCON_DW5_32 (2<<20)
#define S3C2410_BWSCON_WS5 (1<<22)
#define S3C2410_BWSCON_ST5 (1<<23)
/* bank 6 configurations */
#define S3C2410_BWSCON_DW6_8 (0<<24)
#define S3C2410_BWSCON_DW6_16 (1<<24)
#define S3C2410_BWSCON_DW6_32 (2<<24)
#define S3C2410_BWSCON_WS6 (1<<26)
#define S3C2410_BWSCON_ST6 (1<<27)
/* bank 7 configurations */
#define S3C2410_BWSCON_DW7_8 (0<<28)
#define S3C2410_BWSCON_DW7_16 (1<<28)
#define S3C2410_BWSCON_DW7_32 (2<<28)
#define S3C2410_BWSCON_WS7 (1<<30)
#define S3C2410_BWSCON_ST7 (1<<31)
/* accesor functions for getting BANK(n) configuration. (n != 0) */
#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
#define S3C2410_BWSCON_DW8 (0)
#define S3C2410_BWSCON_DW16 (1)
#define S3C2410_BWSCON_DW32 (2)
#define S3C2410_BWSCON_WS (1 << 2)
#define S3C2410_BWSCON_ST (1 << 3)
/* memory set (rom, ram) */
#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C)
#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010)
#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014)
#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018)
#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C)
#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020)
/* bank configuration registers */
#define S3C2410_BANKCON_PMCnorm (0x00)
#define S3C2410_BANKCON_PMC4 (0x01)
#define S3C2410_BANKCON_PMC8 (0x02)
#define S3C2410_BANKCON_PMC16 (0x03)
/* bank configurations for banks 0..7, note banks
* 6 and 7 have different configurations depending on
* the memory type bits */
#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
#define S3C2410_BANKCON_Tacp_SHIFT (2)
#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
#define S3C2410_BANKCON_Tcah_SHIFT (4)
#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
#define S3C2410_BANKCON_Tcoh_SHIFT (6)
#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
#define S3C2410_BANKCON_Tacc3 (0x2 << 8)
#define S3C2410_BANKCON_Tacc4 (0x3 << 8)
#define S3C2410_BANKCON_Tacc6 (0x4 << 8)
#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
#define S3C2410_BANKCON_Tacc_SHIFT (8)
#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
#define S3C2410_BANKCON_Tcos_SHIFT (11)
#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
#define S3C2410_BANKCON_Tacs_SHIFT (13)
#define S3C2410_BANKCON_SRAM (0x0 << 15)
#define S3C2410_BANKCON_SDRAM (0x3 << 15)
/* next bits only for SDRAM in 6,7 */
#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
#define S3C2410_BANKCON_Trcd4 (0x02 << 2)
/* control column address select */
#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
#define S3C2410_BANKCON_SCANb9 (0x01 << 0)
#define S3C2410_BANKCON_SCANb10 (0x02 << 0)
#define S3C2410_REFRESH S3C2410_MEMREG(0x0024)
#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028)
#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C)
#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030)
/* refresh control */
#define S3C2410_REFRESH_REFEN (1<<23)
#define S3C2410_REFRESH_SELF (1<<22)
#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1)
#define S3C2410_REFRESH_TRP_MASK (3<<20)
#define S3C2410_REFRESH_TRP_2clk (0<<20)
#define S3C2410_REFRESH_TRP_3clk (1<<20)
#define S3C2410_REFRESH_TRP_4clk (2<<20)
#define S3C2410_REFRESH_TSRC_MASK (3<<18)
#define S3C2410_REFRESH_TSRC_4clk (0<<18)
#define S3C2410_REFRESH_TSRC_5clk (1<<18)
#define S3C2410_REFRESH_TSRC_6clk (2<<18)
#define S3C2410_REFRESH_TSRC_7clk (3<<18)
/* mode select register(s) */
#define S3C2410_MRSRB_CL1 (0x00 << 4)
#define S3C2410_MRSRB_CL2 (0x02 << 4)
#define S3C2410_MRSRB_CL3 (0x03 << 4)
/* bank size register */
#define S3C2410_BANKSIZE_128M (0x2 << 0)
#define S3C2410_BANKSIZE_64M (0x1 << 0)
#define S3C2410_BANKSIZE_32M (0x0 << 0)
#define S3C2410_BANKSIZE_16M (0x7 << 0)
#define S3C2410_BANKSIZE_8M (0x6 << 0)
#define S3C2410_BANKSIZE_4M (0x5 << 0)
#define S3C2410_BANKSIZE_2M (0x4 << 0)
#define S3C2410_BANKSIZE_MASK (0x7 << 0)
#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
#define S3C2410_BANKSIZE_BURST (1<<7)
#endif /* __ASM_ARM_MEMREGS_H */

40
arch/arm/mach-s3c24xx/include/mach/regs-power.h
View File

@ -1,40 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/regs-power.h
*
* Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C24XX power control register definitions
*/
#ifndef __ASM_ARM_REGS_PWR
#define __ASM_ARM_REGS_PWR __FILE__
#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20)
#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24)
#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70)
#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74)
#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
#define S3C2412_PWRCFG_BATF_IRQ (1<<0)
#define S3C2412_PWRCFG_BATF_IGNORE (2<<0)
#define S3C2412_PWRCFG_BATF_SLEEP (3<<0)
#define S3C2412_PWRCFG_BATF_MASK (3<<0)
#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6)
#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6)
#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6)
#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6)
#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6)
#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8)
#define S3C2412_PWRCFG_NAND_NORST (1<<9)
#endif /* __ASM_ARM_REGS_PWR */

48
arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
View File

@ -1,48 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2412 memory register definitions
*/
#ifndef __ASM_ARM_REGS_S3C2412_MEM
#define __ASM_ARM_REGS_S3C2412_MEM
#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
#define S3C2412_BANKCFG S3C2412_MEMREG(0x00)
#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04)
#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08)
#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C)
#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14)
/* EBI control registers */
#define S3C2412_EBI_PR S3C2412_EBIREG(0x00)
#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04)
/* SSMC control registers */
#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00)
#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00)
#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04)
#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08)
#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C)
#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10)
#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14)
#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18)
#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C)
#endif /* __ASM_ARM_REGS_S3C2412_MEM */

6
arch/arm/plat-s3c24xx/s3c2410-iotiming.c → arch/arm/mach-s3c24xx/iotiming-s3c2410.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
*
/*
* Copyright (c) 2006-2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
@ -20,11 +19,12 @@
#include <linux/slab.h>
#include <mach/map.h>
#include <mach/regs-mem.h>
#include <mach/regs-clock.h>
#include <plat/cpu-freq-core.h>
#include "regs-mem.h"
#define print_ns(x) ((x) / 10), ((x) % 10)
/**

7
arch/arm/plat-s3c24xx/s3c2412-iotiming.c → arch/arm/mach-s3c24xx/iotiming-s3c2412.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
*
/*
* Copyright (c) 2006-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
@ -28,12 +27,12 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/regs-s3c2412-mem.h>
#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>
#include <plat/clock.h>
#include "s3c2412.h"
#define print_ns(x) ((x) / 10), ((x) % 10)
/**

3
arch/arm/mach-s3c24xx/irq-s3c2412.c
View File

@ -33,12 +33,13 @@
#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>
#include <mach/regs-power.h>
#include <plat/cpu.h>
#include <plat/irq.h>
#include <plat/pm.h>
#include "s3c2412-power.h"
#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))

0
arch/arm/plat-s3c24xx/irq.c → arch/arm/mach-s3c24xx/irq.c
View File

1
arch/arm/mach-s3c24xx/mach-anubis.c
View File

@ -34,7 +34,6 @@
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>

1
arch/arm/mach-s3c24xx/mach-at2440evb.c
View File

@ -35,7 +35,6 @@
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>

1
arch/arm/mach-s3c24xx/mach-bast.c
View File

@ -48,7 +48,6 @@
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/regs-mem.h>
#include <plat/clock.h>
#include <plat/cpu.h>

1
arch/arm/mach-s3c24xx/mach-gta02.c
View File

@ -75,7 +75,6 @@
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/regs-irq.h>
#include <mach/regs-mem.h>
#include <plat/cpu.h>
#include <plat/devs.h>

4
arch/arm/mach-s3c24xx/mach-jive.c
View File

@ -35,9 +35,7 @@
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <mach/regs-power.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/fb.h>
@ -56,6 +54,8 @@
#include <plat/pm.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include "s3c2412-power.h"
static struct map_desc jive_iodesc[] __initdata = {
};

1
arch/arm/mach-s3c24xx/mach-mini2440.c
View File

@ -40,7 +40,6 @@
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <linux/platform_data/leds-s3c24xx.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/irqs.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>

2
arch/arm/mach-s3c24xx/mach-osiris.c
View File

@ -47,11 +47,11 @@
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include "common.h"
#include "osiris.h"
#include "regs-mem.h"
/* onboard perihperal map */

2
arch/arm/mach-s3c24xx/pm-s3c2412.c
View File

@ -26,13 +26,13 @@
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/regs-power.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/s3c2412.h>
#include "regs-dsc.h"
#include "s3c2412-power.h"
extern void s3c2412_sleep_enter(void);

3
arch/arm/mach-s3c24xx/pm-s3c2416.c
View File

@ -16,12 +16,13 @@
#include <asm/cacheflush.h>
#include <mach/regs-power.h>
#include <mach/regs-s3c2443-clock.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include "s3c2412-power.h"
extern void s3c2412_sleep_enter(void);
static int s3c2416_cpu_suspend(unsigned long arg)

3
arch/arm/mach-s3c24xx/pm.c
View File

@ -38,7 +38,6 @@
#include <plat/regs-serial.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-irq.h>
#include <asm/mach/time.h>
@ -46,6 +45,8 @@
#include <plat/gpio-cfg.h>
#include <plat/pm.h>
#include "regs-mem.h"
#define PFX "s3c24xx-pm: "
static struct sleep_save core_save[] = {

54
arch/arm/mach-s3c24xx/regs-mem.h Normal file
View File

@ -0,0 +1,54 @@
/*
* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 Memory Control register definitions
*/
#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__
#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#define S3C2410_BWSCON S3C2410_MEMREG(0x00)
#define S3C2410_BANKCON0 S3C2410_MEMREG(0x04)
#define S3C2410_BANKCON1 S3C2410_MEMREG(0x08)
#define S3C2410_BANKCON2 S3C2410_MEMREG(0x0C)
#define S3C2410_BANKCON3 S3C2410_MEMREG(0x10)
#define S3C2410_BANKCON4 S3C2410_MEMREG(0x14)
#define S3C2410_BANKCON5 S3C2410_MEMREG(0x18)
#define S3C2410_BANKCON6 S3C2410_MEMREG(0x1C)
#define S3C2410_BANKCON7 S3C2410_MEMREG(0x20)
#define S3C2410_REFRESH S3C2410_MEMREG(0x24)
#define S3C2410_BANKSIZE S3C2410_MEMREG(0x28)
#define S3C2410_BWSCON_ST1 (1 << 7)
#define S3C2410_BWSCON_ST2 (1 << 11)
#define S3C2410_BWSCON_ST3 (1 << 15)
#define S3C2410_BWSCON_ST4 (1 << 19)
#define S3C2410_BWSCON_ST5 (1 << 23)
#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
#define S3C2410_BWSCON_WS (1 << 2)
#define S3C2410_BANKCON_PMC16 (0x3)
#define S3C2410_BANKCON_Tacp_SHIFT (2)
#define S3C2410_BANKCON_Tcah_SHIFT (4)
#define S3C2410_BANKCON_Tcoh_SHIFT (6)
#define S3C2410_BANKCON_Tacc_SHIFT (8)
#define S3C2410_BANKCON_Tcos_SHIFT (11)
#define S3C2410_BANKCON_Tacs_SHIFT (13)
#define S3C2410_BANKCON_SDRAM (0x3 << 15)
#define S3C2410_REFRESH_SELF (1 << 22)
#define S3C2410_BANKSIZE_MASK (0x7 << 0)
#endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */

37
arch/arm/mach-s3c24xx/s3c2412-power.h Normal file
View File

@ -0,0 +1,37 @@
/*
* Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H
#define __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H __FILE__
#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20)
#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24)
#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70)
#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74)
#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
#define S3C2412_PWRCFG_BATF_IRQ (1 << 0)
#define S3C2412_PWRCFG_BATF_IGNORE (2 << 0)
#define S3C2412_PWRCFG_BATF_SLEEP (3 << 0)
#define S3C2412_PWRCFG_BATF_MASK (3 << 0)
#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0 << 6)
#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1 << 6)
#define S3C2412_PWRCFG_STANDBYWFI_STOP (2 << 6)
#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3 << 6)
#define S3C2412_PWRCFG_STANDBYWFI_MASK (3 << 6)
#define S3C2412_PWRCFG_RTC_MASKIRQ (1 << 8)
#define S3C2412_PWRCFG_NAND_NORST (1 << 9)
#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H */

2
arch/arm/mach-s3c24xx/s3c2412.c
View File

@ -34,7 +34,6 @@
#include <mach/hardware.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <mach/regs-power.h>
#include <plat/clock.h>
#include <plat/cpu.h>
@ -49,6 +48,7 @@
#include "common.h"
#include "regs-dsc.h"
#include "s3c2412-power.h"
#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
#define S3C2412_SWRST_RESET (0x533C2412)

26
arch/arm/mach-s3c24xx/s3c2412.h Normal file
View File

@ -0,0 +1,26 @@
/*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H
#define __ARCH_ARM_REGS_S3C24XX_S3C2412_H __FILE__
#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x4)
#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x0)
#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */

3
arch/arm/mach-s3c24xx/simtec-pm.c
View File

@ -28,12 +28,13 @@
#include <mach/map.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <asm/mach-types.h>
#include <plat/pm.h>
#include "regs-mem.h"
#define COPYRIGHT ", Copyright 2005 Simtec Electronics"
/* pm_simtec_init

3
arch/arm/mach-s3c24xx/sleep-s3c2410.S
View File

@ -31,9 +31,10 @@
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/regs-mem.h>
#include <plat/regs-serial.h>
#include "regs-mem.h"
/* s3c2410_cpu_suspend
*
* put the cpu into sleep mode

1
arch/arm/mach-s3c24xx/sleep.S
View File

@ -31,7 +31,6 @@
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/regs-mem.h>
#include <plat/regs-serial.h>
/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not

117
arch/arm/plat-s3c24xx/Kconfig
View File

@ -1,117 +0,0 @@
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2
config PLAT_S3C24XX
bool
depends on ARCH_S3C24XX
default y
select ARCH_REQUIRE_GPIOLIB
select NO_IOPORT
select S3C_DEV_NAND
select IRQ_DOMAIN
help
Base platform code for any Samsung S3C24XX device
if PLAT_S3C24XX
# low-level serial option nodes
config CPU_LLSERIAL_S3C2410_ONLY
bool
default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
config CPU_LLSERIAL_S3C2440_ONLY
bool
default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
config CPU_LLSERIAL_S3C2410
bool
help
Selected if there is an S3C2410 (or register compatible) serial
low-level implementation needed
config CPU_LLSERIAL_S3C2440
bool
help
Selected if there is an S3C2440 (or register compatible) serial
low-level implementation needed
# code that is shared between a number of the s3c24xx implementations
config S3C2410_CLOCK
bool
help
Clock code for the S3C2410, and similar processors which
is currently includes the S3C2410, S3C2440, S3C2442.
config S3C24XX_DCLK
bool
help
Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
# gpio configurations
config S3C24XX_GPIO_EXTRA
int
default 128 if S3C24XX_GPIO_EXTRA128
default 64 if S3C24XX_GPIO_EXTRA64
default 16 if ARCH_H1940
default 0
config S3C24XX_GPIO_EXTRA64
bool
help
Add an extra 64 gpio numbers to the available GPIO pool. This is
available for boards that need extra gpios for external devices.
config S3C24XX_GPIO_EXTRA128
bool
help
Add an extra 128 gpio numbers to the available GPIO pool. This is
available for boards that need extra gpios for external devices.
config S3C24XX_DMA
bool "S3C2410 DMA support"
depends on ARCH_S3C24XX
select S3C_DMA
help
S3C2410 DMA support. This is needed for drivers like sound which
use the S3C2410's DMA system to move data to and from the
peripheral blocks.
config S3C2410_DMA_DEBUG
bool "S3C2410 DMA support debug"
depends on ARCH_S3C24XX && S3C2410_DMA
help
Enable debugging output for the DMA code. This option sends info
to the kernel log, at priority KERN_DEBUG.
# common code for s3c24xx based machines, such as the SMDKs.
# cpu frequency items common between s3c2410 and s3c2440/s3c2442
config S3C2410_IOTIMING
bool
depends on CPU_FREQ_S3C24XX
help
Internal node to select io timing code that is common to the s3c2410
and s3c2440/s3c2442 cpu frequency support.
config S3C2410_CPUFREQ_UTILS
bool
depends on CPU_FREQ_S3C24XX
help
Internal node to select timing code that is common to the s3c2410
and s3c2440/s3c244 cpu frequency support.
# cpu frequency support common to s3c2412, s3c2413 and s3c2442
config S3C2412_IOTIMING
bool
depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
help
Intel node to select io timing code that is common to the s3c2412
and the s3c2443.
endif

27
arch/arm/plat-s3c24xx/Makefile
View File

@ -1,27 +0,0 @@
# arch/arm/plat-s3c24xx/Makefile
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core files
obj-y += irq.o
obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o
obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
# Architecture dependent builds
obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
obj-$(CONFIG_S3C24XX_DMA) += dma.o
obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o
obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o
obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o