ARM: LPC32xx: Fix missing and bad LPC32XX macros
Some of the LPC32XX_* macros were typed ("LCP32XX_*"), which is fixed by this
patch. (Besides another LCP doc typo.)
Further, the LPC32XX_GPIO_P2_MUX_SET/CLR/STATE macros were missing.
Signed-off-by: Roland Stigge <stigge@antcom.de>
This commit is contained in:
Roland Stigge
parent
6b21d18ed5
commit
cfac337b0f
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@ -591,42 +591,42 @@
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/*
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* Timer/counter register offsets
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*/
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#define LCP32XX_TIMER_IR(x) io_p2v((x) + 0x00)
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#define LCP32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
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#define LCP32XX_TIMER_TC(x) io_p2v((x) + 0x08)
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#define LCP32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
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#define LCP32XX_TIMER_PC(x) io_p2v((x) + 0x10)
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#define LCP32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
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#define LCP32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
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#define LCP32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
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#define LCP32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
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#define LCP32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
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#define LCP32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
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#define LCP32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
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#define LCP32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
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#define LCP32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
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#define LCP32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
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#define LCP32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
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#define LCP32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
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#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00)
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#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
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#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08)
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#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
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#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10)
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#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
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#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
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#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
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#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
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#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
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#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
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#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
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#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
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#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
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#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
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#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
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#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
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/*
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* ir register definitions
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*/
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#define LCP32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
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#define LCP32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
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#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
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#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
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/*
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* tcr register definitions
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*/
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#define LCP32XX_TIMER_CNTR_TCR_EN 0x1
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#define LCP32XX_TIMER_CNTR_TCR_RESET 0x2
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#define LPC32XX_TIMER_CNTR_TCR_EN 0x1
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#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2
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/*
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* mcr register definitions
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*/
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#define LCP32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
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#define LCP32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
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#define LCP32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
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#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
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#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
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#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
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/*
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* Standard UART register offsets
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@ -690,5 +690,8 @@
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#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130)
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#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134)
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#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138)
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#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
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#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
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#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
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#endif
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@ -13,7 +13,7 @@
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/*
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* LPC32XX CPU and system power management
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*
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* The LCP32XX has three CPU modes for controlling system power: run,
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* The LPC32XX has three CPU modes for controlling system power: run,
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* direct-run, and halt modes. When switching between halt and run modes,
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* the CPU transistions through direct-run mode. For Linux, direct-run
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* mode is not used in normal operation. Halt mode is used when the
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@ -34,11 +34,11 @@
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static int lpc32xx_clkevt_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
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LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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__raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
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__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
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LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
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LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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__raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
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LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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return 0;
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}
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@ -58,7 +58,7 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
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* disable the timer to wait for the first call to
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* set_next_event().
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*/
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__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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break;
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case CLOCK_EVT_MODE_UNUSED:
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@ -81,8 +81,8 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
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struct clock_event_device *evt = &lpc32xx_clkevt;
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/* Clear match */
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__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
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LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
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LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
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evt->event_handler(evt);
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@ -128,14 +128,14 @@ static void __init lpc32xx_timer_init(void)
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clkrate = clkrate / clk_get_pclk_div();
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/* Initial timer setup */
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__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
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LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
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__raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
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__raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
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LCP32XX_TIMER_CNTR_MCR_STOP(0) |
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LCP32XX_TIMER_CNTR_MCR_RESET(0),
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LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
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__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
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LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
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__raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
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LPC32XX_TIMER_CNTR_MCR_STOP(0) |
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LPC32XX_TIMER_CNTR_MCR_RESET(0),
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LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
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/* Setup tick interrupt */
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setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
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@ -151,14 +151,14 @@ static void __init lpc32xx_timer_init(void)
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clockevents_register_device(&lpc32xx_clkevt);
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/* Use timer1 as clock source. */
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__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
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LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
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__raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
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__raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
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__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
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LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
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LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
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__raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
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__raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
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LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
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clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
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clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
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"lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
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}
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