mfd: Add support for ams AS3722 PMIC
The ams AS3722 is a compact system PMU suitable for mobile phones, tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down controller, 11 LDOs, RTC, automatic battery, temperature and over-current monitoring, 8 GPIOs, ADC and a watchdog. Add MFD core driver for the AS3722 to support core functionality. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Florian Lobmaier <florian.lobmaier@ams.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Laxman Dewangan
Lee Jones
parent
71c7f93ea0
commit
d460a6f3d6
194
Documentation/devicetree/bindings/mfd/as3722.txt
Normal file
194
Documentation/devicetree/bindings/mfd/as3722.txt
Normal file
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@ -0,0 +1,194 @@
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* ams AS3722 Power management IC.
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Required properties:
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-------------------
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- compatible: Must be "ams,as3722".
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- reg: I2C device address.
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- interrupt-controller: AS3722 has internal interrupt controller which takes the
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interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
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as external input.
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- #interrupt-cells: Should be set to 2 for IRQ number and flags.
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The first cell is the IRQ number. IRQ numbers for different interrupt source
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of AS3722 are defined at dt-bindings/mfd/as3722.h
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The second cell is the flags, encoded as the trigger masks from binding document
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interrupts.txt, using dt-bindings/irq.
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Optional submodule and their properties:
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=======================================
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Pinmux and GPIO:
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===============
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Device has 8 GPIO pins which can be configured as GPIO as well as the special IO
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functions.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Following are properties which is needed if GPIO and pinmux functionality
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is required:
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Required properties:
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-------------------
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells: Number of GPIO cells. Refer to binding document
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gpio/gpio.txt
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Optional properties:
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--------------------
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Following properties are require if pin control setting is required
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at boot.
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- pinctrl-names: A pinctrl state named "default" be defined, using the
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bindings in pinctrl/pinctrl-binding.txt.
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- pinctrl[0...n]: Properties to contain the phandle that refer to
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different nodes of pin control settings. These nodes represents
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the pin control setting of state 0 to state n. Each of these
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nodes contains different subnodes to represents some desired
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configuration for a list of pins. This configuration can
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include the mux function to select on those pin(s), and
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various pin configuration parameters, such as pull-up,
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open drain.
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Each subnode have following properties:
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Required properties:
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- pins: List of pins. Valid values of pins properties are:
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gpio0, gpio1, gpio2, gpio3, gpio4, gpio5,
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gpio6, gpio7
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Optional properties:
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function, bias-disable, bias-pull-up, bias-pull-down,
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bias-high-impedance, drive-open-drain.
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Valid values for function properties are:
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gpio, interrupt-out, gpio-in-interrupt,
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vsup-vbat-low-undebounce-out,
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vsup-vbat-low-debounce-out,
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voltage-in-standby, oc-pg-sd0, oc-pg-sd6,
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powergood-out, pwm-in, pwm-out, clk32k-out,
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watchdog-in, soft-reset-in
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Regulators:
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===========
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Device has multiple DCDC and LDOs. The node "regulators" is require if regulator
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functionality is needed.
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Following are properties of regulator subnode.
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Optional properties:
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-------------------
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The input supply of regulators are the optional properties on the
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regulator node. The input supply of these regulators are provided
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through following properties:
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vsup-sd2-supply: Input supply for SD2.
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vsup-sd3-supply: Input supply for SD3.
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vsup-sd4-supply: Input supply for SD4.
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vsup-sd5-supply: Input supply for SD5.
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vin-ldo0-supply: Input supply for LDO0.
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vin-ldo1-6-supply: Input supply for LDO1 and LDO6.
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vin-ldo2-5-7-supply: Input supply for LDO2, LDO5 and LDO7.
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vin-ldo3-4-supply: Input supply for LDO3 and LDO4.
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vin-ldo9-10-supply: Input supply for LDO9 and LDO10.
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vin-ldo11-supply: Input supply for LDO11.
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Optional sub nodes for regulators:
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---------------------------------
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The subnodes name is the name of regulator and it must be one of:
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sd[0-6], ldo[0-7], ldo[9-11]
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Each sub-node should contain the constraints and initialization
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information for that regulator. See regulator.txt for a description
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of standard properties for these sub-nodes.
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Additional optional custom properties are listed below.
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ams,ext-control: External control of the rail. The option of
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this properties will tell which external input is
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controlling this rail. Valid values are 0, 1, 2 ad 3.
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0: There is no external control of this rail.
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1: Rail is controlled by ENABLE1 input pin.
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2: Rail is controlled by ENABLE2 input pin.
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3: Rail is controlled by ENABLE3 input pin.
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Missing this property on DT will be assume as no
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external control. The external control pin macros
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are defined @dt-bindings/mfd/as3722.h
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ams,enable-tracking: Enable tracking with SD1, only supported
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by LDO3.
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Example:
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--------
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#include <dt-bindings/mfd/as3722.h>
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...
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ams3722 {
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compatible = "ams,as3722";
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reg = <0x48>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&as3722_default>;
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as3722_default: pinmux {
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gpio0 {
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pins = "gpio0";
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function = "gpio";
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bias-pull-down;
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};
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gpio1_2_4_7 {
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pins = "gpio1", "gpio2", "gpio4", "gpio7";
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function = "gpio";
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bias-pull-up;
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};
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gpio5 {
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pins = "gpio5";
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function = "clk32k_out";
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};
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}
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regulators {
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vsup-sd2-supply = <...>;
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...
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sd0 {
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regulator-name = "vdd_cpu";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1400000>;
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regulator-always-on;
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ams,ext-control = <2>;
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};
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sd1 {
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regulator-name = "vdd_core";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1400000>;
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regulator-always-on;
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ams,ext-control = <1>;
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};
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sd2 {
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regulator-name = "vddio_ddr";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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};
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sd4 {
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regulator-name = "avdd-hdmi-pex";
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regulator-min-microvolt = <1050000>;
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regulator-max-microvolt = <1050000>;
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regulator-always-on;
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};
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sd5 {
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regulator-name = "vdd-1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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....
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};
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};
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@ -27,6 +27,18 @@ config MFD_AS3711
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help
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Support for the AS3711 PMIC from AMS
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config MFD_AS3722
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bool "ams AS3722 Power Management IC"
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select MFD_CORE
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select REGMAP_I2C
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select REGMAP_IRQ
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depends on I2C && OF
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help
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The ams AS3722 is a compact system PMU suitable for mobile phones,
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tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down
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controllers, 11 LDOs, RTC, automatic battery, temperature and
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over current monitoring, GPIOs, ADC and a watchdog.
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config PMIC_ADP5520
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bool "Analog Devices ADP5520/01 MFD PMIC Core Support"
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depends on I2C=y
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@ -162,4 +162,5 @@ obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o
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obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o vexpress-sysreg.o
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obj-$(CONFIG_MFD_RETU) += retu-mfd.o
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obj-$(CONFIG_MFD_AS3711) += as3711.o
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obj-$(CONFIG_MFD_AS3722) += as3722.o
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obj-$(CONFIG_MFD_STW481X) += stw481x.o
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449
drivers/mfd/as3722.c
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449
drivers/mfd/as3722.c
Normal file
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@ -0,0 +1,449 @@
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/*
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* Core driver for ams AS3722 PMICs
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*
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* Copyright (C) 2013 AMS AG
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* Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
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*
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* Author: Florian Lobmaier <florian.lobmaier@ams.com>
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* Author: Laxman Dewangan <ldewangan@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/as3722.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#define AS3722_DEVICE_ID 0x0C
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static const struct resource as3722_rtc_resource[] = {
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{
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.name = "as3722-rtc-alarm",
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.start = AS3722_IRQ_RTC_ALARM,
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.end = AS3722_IRQ_RTC_ALARM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static const struct resource as3722_adc_resource[] = {
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{
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.name = "as3722-adc",
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.start = AS3722_IRQ_ADC,
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.end = AS3722_IRQ_ADC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct mfd_cell as3722_devs[] = {
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{
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.name = "as3722-pinctrl",
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},
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{
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.name = "as3722-regulator",
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},
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{
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.name = "as3722-rtc",
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.num_resources = ARRAY_SIZE(as3722_rtc_resource),
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.resources = as3722_rtc_resource,
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},
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{
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.name = "as3722-adc",
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.num_resources = ARRAY_SIZE(as3722_adc_resource),
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.resources = as3722_adc_resource,
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},
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{
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.name = "as3722-power-off",
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},
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};
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static const struct regmap_irq as3722_irqs[] = {
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/* INT1 IRQs */
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[AS3722_IRQ_LID] = {
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.mask = AS3722_INTERRUPT_MASK1_LID,
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},
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[AS3722_IRQ_ACOK] = {
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.mask = AS3722_INTERRUPT_MASK1_ACOK,
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},
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[AS3722_IRQ_ENABLE1] = {
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.mask = AS3722_INTERRUPT_MASK1_ENABLE1,
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},
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[AS3722_IRQ_OCCUR_ALARM_SD0] = {
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.mask = AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0,
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},
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[AS3722_IRQ_ONKEY_LONG_PRESS] = {
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.mask = AS3722_INTERRUPT_MASK1_ONKEY_LONG,
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},
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[AS3722_IRQ_ONKEY] = {
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.mask = AS3722_INTERRUPT_MASK1_ONKEY,
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},
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[AS3722_IRQ_OVTMP] = {
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.mask = AS3722_INTERRUPT_MASK1_OVTMP,
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},
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[AS3722_IRQ_LOWBAT] = {
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.mask = AS3722_INTERRUPT_MASK1_LOWBAT,
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},
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/* INT2 IRQs */
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[AS3722_IRQ_SD0_LV] = {
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.mask = AS3722_INTERRUPT_MASK2_SD0_LV,
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.reg_offset = 1,
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},
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[AS3722_IRQ_SD1_LV] = {
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.mask = AS3722_INTERRUPT_MASK2_SD1_LV,
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.reg_offset = 1,
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},
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[AS3722_IRQ_SD2_LV] = {
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.mask = AS3722_INTERRUPT_MASK2_SD2345_LV,
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.reg_offset = 1,
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},
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[AS3722_IRQ_PWM1_OV_PROT] = {
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.mask = AS3722_INTERRUPT_MASK2_PWM1_OV_PROT,
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.reg_offset = 1,
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},
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[AS3722_IRQ_PWM2_OV_PROT] = {
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.mask = AS3722_INTERRUPT_MASK2_PWM2_OV_PROT,
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.reg_offset = 1,
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},
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[AS3722_IRQ_ENABLE2] = {
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.mask = AS3722_INTERRUPT_MASK2_ENABLE2,
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.reg_offset = 1,
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},
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[AS3722_IRQ_SD6_LV] = {
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.mask = AS3722_INTERRUPT_MASK2_SD6_LV,
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.reg_offset = 1,
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},
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[AS3722_IRQ_RTC_REP] = {
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.mask = AS3722_INTERRUPT_MASK2_RTC_REP,
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.reg_offset = 1,
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},
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/* INT3 IRQs */
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[AS3722_IRQ_RTC_ALARM] = {
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.mask = AS3722_INTERRUPT_MASK3_RTC_ALARM,
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.reg_offset = 2,
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},
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[AS3722_IRQ_GPIO1] = {
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.mask = AS3722_INTERRUPT_MASK3_GPIO1,
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.reg_offset = 2,
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},
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[AS3722_IRQ_GPIO2] = {
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.mask = AS3722_INTERRUPT_MASK3_GPIO2,
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.reg_offset = 2,
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},
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[AS3722_IRQ_GPIO3] = {
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.mask = AS3722_INTERRUPT_MASK3_GPIO3,
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.reg_offset = 2,
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},
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[AS3722_IRQ_GPIO4] = {
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.mask = AS3722_INTERRUPT_MASK3_GPIO4,
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.reg_offset = 2,
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},
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[AS3722_IRQ_GPIO5] = {
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.mask = AS3722_INTERRUPT_MASK3_GPIO5,
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.reg_offset = 2,
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},
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[AS3722_IRQ_WATCHDOG] = {
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.mask = AS3722_INTERRUPT_MASK3_WATCHDOG,
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.reg_offset = 2,
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},
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[AS3722_IRQ_ENABLE3] = {
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.mask = AS3722_INTERRUPT_MASK3_ENABLE3,
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.reg_offset = 2,
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},
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/* INT4 IRQs */
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[AS3722_IRQ_TEMP_SD0_SHUTDOWN] = {
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.mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN,
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.reg_offset = 3,
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},
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[AS3722_IRQ_TEMP_SD1_SHUTDOWN] = {
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.mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN,
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.reg_offset = 3,
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},
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[AS3722_IRQ_TEMP_SD2_SHUTDOWN] = {
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.mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN,
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.reg_offset = 3,
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},
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[AS3722_IRQ_TEMP_SD0_ALARM] = {
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.mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM,
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.reg_offset = 3,
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},
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[AS3722_IRQ_TEMP_SD1_ALARM] = {
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.mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM,
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.reg_offset = 3,
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},
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[AS3722_IRQ_TEMP_SD6_ALARM] = {
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.mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM,
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.reg_offset = 3,
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},
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[AS3722_IRQ_OCCUR_ALARM_SD6] = {
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.mask = AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6,
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.reg_offset = 3,
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},
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[AS3722_IRQ_ADC] = {
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.mask = AS3722_INTERRUPT_MASK4_ADC,
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.reg_offset = 3,
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},
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};
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static const struct regmap_irq_chip as3722_irq_chip = {
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.name = "as3722",
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.irqs = as3722_irqs,
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.num_irqs = ARRAY_SIZE(as3722_irqs),
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.num_regs = 4,
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.status_base = AS3722_INTERRUPT_STATUS1_REG,
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.mask_base = AS3722_INTERRUPT_MASK1_REG,
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};
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static int as3722_check_device_id(struct as3722 *as3722)
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{
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
/* Check that this is actually a AS3722 */
|
||||
ret = as3722_read(as3722, AS3722_ASIC_ID1_REG, &val);
|
||||
if (ret < 0) {
|
||||
dev_err(as3722->dev, "ASIC_ID1 read failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (val != AS3722_DEVICE_ID) {
|
||||
dev_err(as3722->dev, "Device is not AS3722, ID is 0x%x\n", val);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = as3722_read(as3722, AS3722_ASIC_ID2_REG, &val);
|
||||
if (ret < 0) {
|
||||
dev_err(as3722->dev, "ASIC_ID2 read failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(as3722->dev, "AS3722 with revision 0x%x found\n", val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int as3722_configure_pullups(struct as3722 *as3722)
|
||||
{
|
||||
int ret;
|
||||
u32 val = 0;
|
||||
|
||||
if (as3722->en_intern_int_pullup)
|
||||
val |= AS3722_INT_PULL_UP;
|
||||
if (as3722->en_intern_i2c_pullup)
|
||||
val |= AS3722_I2C_PULL_UP;
|
||||
|
||||
ret = as3722_update_bits(as3722, AS3722_IOVOLTAGE_REG,
|
||||
AS3722_INT_PULL_UP | AS3722_I2C_PULL_UP, val);
|
||||
if (ret < 0)
|
||||
dev_err(as3722->dev, "IOVOLTAGE_REG update failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct regmap_range as3722_readable_ranges[] = {
|
||||
regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_SD6_VOLTAGE_REG),
|
||||
regmap_reg_range(AS3722_GPIO0_CONTROL_REG, AS3722_LDO7_VOLTAGE_REG),
|
||||
regmap_reg_range(AS3722_LDO9_VOLTAGE_REG, AS3722_REG_SEQU_MOD3_REG),
|
||||
regmap_reg_range(AS3722_SD_PHSW_CTRL_REG, AS3722_PWM_CONTROL_H_REG),
|
||||
regmap_reg_range(AS3722_WATCHDOG_TIMER_REG, AS3722_WATCHDOG_TIMER_REG),
|
||||
regmap_reg_range(AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG,
|
||||
AS3722_BATTERY_VOLTAGE_MONITOR2_REG),
|
||||
regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_PWM_VCONTROL4_REG),
|
||||
regmap_reg_range(AS3722_BB_CHARGER_REG, AS3722_SRAM_REG),
|
||||
regmap_reg_range(AS3722_RTC_ACCESS_REG, AS3722_RTC_ACCESS_REG),
|
||||
regmap_reg_range(AS3722_RTC_STATUS_REG, AS3722_TEMP_STATUS_REG),
|
||||
regmap_reg_range(AS3722_ADC0_CONTROL_REG, AS3722_ADC_CONFIGURATION_REG),
|
||||
regmap_reg_range(AS3722_ASIC_ID1_REG, AS3722_ASIC_ID2_REG),
|
||||
regmap_reg_range(AS3722_LOCK_REG, AS3722_LOCK_REG),
|
||||
};
|
||||
|
||||
static const struct regmap_access_table as3722_readable_table = {
|
||||
.yes_ranges = as3722_readable_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(as3722_readable_ranges),
|
||||
};
|
||||
|
||||
static const struct regmap_range as3722_writable_ranges[] = {
|
||||
regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_SD6_VOLTAGE_REG),
|
||||
regmap_reg_range(AS3722_GPIO0_CONTROL_REG, AS3722_LDO7_VOLTAGE_REG),
|
||||
regmap_reg_range(AS3722_LDO9_VOLTAGE_REG, AS3722_GPIO_SIGNAL_OUT_REG),
|
||||
regmap_reg_range(AS3722_REG_SEQU_MOD1_REG, AS3722_REG_SEQU_MOD3_REG),
|
||||
regmap_reg_range(AS3722_SD_PHSW_CTRL_REG, AS3722_PWM_CONTROL_H_REG),
|
||||
regmap_reg_range(AS3722_WATCHDOG_TIMER_REG, AS3722_WATCHDOG_TIMER_REG),
|
||||
regmap_reg_range(AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG,
|
||||
AS3722_BATTERY_VOLTAGE_MONITOR2_REG),
|
||||
regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_PWM_VCONTROL4_REG),
|
||||
regmap_reg_range(AS3722_BB_CHARGER_REG, AS3722_SRAM_REG),
|
||||
regmap_reg_range(AS3722_INTERRUPT_MASK1_REG, AS3722_TEMP_STATUS_REG),
|
||||
regmap_reg_range(AS3722_ADC0_CONTROL_REG, AS3722_ADC1_CONTROL_REG),
|
||||
regmap_reg_range(AS3722_ADC1_THRESHOLD_HI_MSB_REG,
|
||||
AS3722_ADC_CONFIGURATION_REG),
|
||||
regmap_reg_range(AS3722_LOCK_REG, AS3722_LOCK_REG),
|
||||
};
|
||||
|
||||
static const struct regmap_access_table as3722_writable_table = {
|
||||
.yes_ranges = as3722_writable_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(as3722_writable_ranges),
|
||||
};
|
||||
|
||||
static const struct regmap_range as3722_cacheable_ranges[] = {
|
||||
regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_LDO11_VOLTAGE_REG),
|
||||
regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_LDOCONTROL1_REG),
|
||||
};
|
||||
|
||||
static const struct regmap_access_table as3722_volatile_table = {
|
||||
.no_ranges = as3722_cacheable_ranges,
|
||||
.n_no_ranges = ARRAY_SIZE(as3722_cacheable_ranges),
|
||||
};
|
||||
|
||||
const struct regmap_config as3722_regmap_config = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
.max_register = AS3722_MAX_REGISTER,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.rd_table = &as3722_readable_table,
|
||||
.wr_table = &as3722_writable_table,
|
||||
.volatile_table = &as3722_volatile_table,
|
||||
};
|
||||
|
||||
static int as3722_i2c_of_probe(struct i2c_client *i2c,
|
||||
struct as3722 *as3722)
|
||||
{
|
||||
struct device_node *np = i2c->dev.of_node;
|
||||
struct irq_data *irq_data;
|
||||
|
||||
if (!np) {
|
||||
dev_err(&i2c->dev, "Device Tree not found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
irq_data = irq_get_irq_data(i2c->irq);
|
||||
if (!irq_data) {
|
||||
dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
as3722->en_intern_int_pullup = of_property_read_bool(np,
|
||||
"ams,enable-internal-int-pullup");
|
||||
as3722->en_intern_i2c_pullup = of_property_read_bool(np,
|
||||
"ams,enable-internal-i2c-pullup");
|
||||
as3722->irq_flags = irqd_get_trigger_type(irq_data);
|
||||
dev_dbg(&i2c->dev, "IRQ flags are 0x%08lx\n", as3722->irq_flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int as3722_i2c_probe(struct i2c_client *i2c,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct as3722 *as3722;
|
||||
unsigned long irq_flags;
|
||||
int ret;
|
||||
|
||||
as3722 = devm_kzalloc(&i2c->dev, sizeof(struct as3722), GFP_KERNEL);
|
||||
if (!as3722)
|
||||
return -ENOMEM;
|
||||
|
||||
as3722->dev = &i2c->dev;
|
||||
as3722->chip_irq = i2c->irq;
|
||||
i2c_set_clientdata(i2c, as3722);
|
||||
|
||||
ret = as3722_i2c_of_probe(i2c, as3722);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
as3722->regmap = devm_regmap_init_i2c(i2c, &as3722_regmap_config);
|
||||
if (IS_ERR(as3722->regmap)) {
|
||||
ret = PTR_ERR(as3722->regmap);
|
||||
dev_err(&i2c->dev, "regmap init failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = as3722_check_device_id(as3722);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
irq_flags = as3722->irq_flags | IRQF_ONESHOT;
|
||||
ret = regmap_add_irq_chip(as3722->regmap, as3722->chip_irq,
|
||||
irq_flags, -1, &as3722_irq_chip,
|
||||
&as3722->irq_data);
|
||||
if (ret < 0) {
|
||||
dev_err(as3722->dev, "Failed to add regmap irq: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = as3722_configure_pullups(as3722);
|
||||
if (ret < 0)
|
||||
goto scrub;
|
||||
|
||||
ret = mfd_add_devices(&i2c->dev, -1, as3722_devs,
|
||||
ARRAY_SIZE(as3722_devs), NULL, 0,
|
||||
regmap_irq_get_domain(as3722->irq_data));
|
||||
if (ret) {
|
||||
dev_err(as3722->dev, "Failed to add MFD devices: %d\n", ret);
|
||||
goto scrub;
|
||||
}
|
||||
|
||||
dev_dbg(as3722->dev, "AS3722 core driver initialized successfully\n");
|
||||
return 0;
|
||||
|
||||
scrub:
|
||||
regmap_del_irq_chip(as3722->chip_irq, as3722->irq_data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int as3722_i2c_remove(struct i2c_client *i2c)
|
||||
{
|
||||
struct as3722 *as3722 = i2c_get_clientdata(i2c);
|
||||
|
||||
mfd_remove_devices(as3722->dev);
|
||||
regmap_del_irq_chip(as3722->chip_irq, as3722->irq_data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id as3722_of_match[] = {
|
||||
{ .compatible = "ams,as3722", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, as3722_of_match);
|
||||
|
||||
static const struct i2c_device_id as3722_i2c_id[] = {
|
||||
{ "as3722", 0 },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, as3722_i2c_id);
|
||||
|
||||
static struct i2c_driver as3722_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "as3722",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = as3722_of_match,
|
||||
},
|
||||
.probe = as3722_i2c_probe,
|
||||
.remove = as3722_i2c_remove,
|
||||
.id_table = as3722_i2c_id,
|
||||
};
|
||||
|
||||
module_i2c_driver(as3722_i2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("I2C support for AS3722 PMICs");
|
||||
MODULE_AUTHOR("Florian Lobmaier <florian.lobmaier@ams.com>");
|
||||
MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
52
include/dt-bindings/mfd/as3722.h
Normal file
52
include/dt-bindings/mfd/as3722.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* This header provides macros for ams AS3722 device bindings.
|
||||
*
|
||||
* Copyright (c) 2013, NVIDIA Corporation.
|
||||
*
|
||||
* Author: Laxman Dewangan <ldewangan@nvidia.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_AS3722_H__
|
||||
#define __DT_BINDINGS_AS3722_H__
|
||||
|
||||
/* External control pins */
|
||||
#define AS3722_EXT_CONTROL_PIN_ENABLE1 1
|
||||
#define AS3722_EXT_CONTROL_PIN_ENABLE2 2
|
||||
#define AS3722_EXT_CONTROL_PIN_ENABLE2 3
|
||||
|
||||
/* Interrupt numbers for AS3722 */
|
||||
#define AS3722_IRQ_LID 0
|
||||
#define AS3722_IRQ_ACOK 1
|
||||
#define AS3722_IRQ_ENABLE1 2
|
||||
#define AS3722_IRQ_OCCUR_ALARM_SD0 3
|
||||
#define AS3722_IRQ_ONKEY_LONG_PRESS 4
|
||||
#define AS3722_IRQ_ONKEY 5
|
||||
#define AS3722_IRQ_OVTMP 6
|
||||
#define AS3722_IRQ_LOWBAT 7
|
||||
#define AS3722_IRQ_SD0_LV 8
|
||||
#define AS3722_IRQ_SD1_LV 9
|
||||
#define AS3722_IRQ_SD2_LV 10
|
||||
#define AS3722_IRQ_PWM1_OV_PROT 11
|
||||
#define AS3722_IRQ_PWM2_OV_PROT 12
|
||||
#define AS3722_IRQ_ENABLE2 13
|
||||
#define AS3722_IRQ_SD6_LV 14
|
||||
#define AS3722_IRQ_RTC_REP 15
|
||||
#define AS3722_IRQ_RTC_ALARM 16
|
||||
#define AS3722_IRQ_GPIO1 17
|
||||
#define AS3722_IRQ_GPIO2 18
|
||||
#define AS3722_IRQ_GPIO3 19
|
||||
#define AS3722_IRQ_GPIO4 20
|
||||
#define AS3722_IRQ_GPIO5 21
|
||||
#define AS3722_IRQ_WATCHDOG 22
|
||||
#define AS3722_IRQ_ENABLE3 23
|
||||
#define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24
|
||||
#define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25
|
||||
#define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26
|
||||
#define AS3722_IRQ_TEMP_SD0_ALARM 27
|
||||
#define AS3722_IRQ_TEMP_SD1_ALARM 28
|
||||
#define AS3722_IRQ_TEMP_SD6_ALARM 29
|
||||
#define AS3722_IRQ_OCCUR_ALARM_SD6 30
|
||||
#define AS3722_IRQ_ADC 31
|
||||
|
||||
#endif /* __DT_BINDINGS_AS3722_H__ */
|
||||
423
include/linux/mfd/as3722.h
Normal file
423
include/linux/mfd/as3722.h
Normal file
|
|
@ -0,0 +1,423 @@
|
|||
/*
|
||||
* as3722 definitions
|
||||
*
|
||||
* Copyright (C) 2013 ams
|
||||
* Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* Author: Florian Lobmaier <florian.lobmaier@ams.com>
|
||||
* Author: Laxman Dewangan <ldewangan@nvidia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_AS3722_H__
|
||||
#define __LINUX_MFD_AS3722_H__
|
||||
|
||||
#include <linux/regmap.h>
|
||||
|
||||
/* AS3722 registers */
|
||||
#define AS3722_SD0_VOLTAGE_REG 0x00
|
||||
#define AS3722_SD1_VOLTAGE_REG 0x01
|
||||
#define AS3722_SD2_VOLTAGE_REG 0x02
|
||||
#define AS3722_SD3_VOLTAGE_REG 0x03
|
||||
#define AS3722_SD4_VOLTAGE_REG 0x04
|
||||
#define AS3722_SD5_VOLTAGE_REG 0x05
|
||||
#define AS3722_SD6_VOLTAGE_REG 0x06
|
||||
#define AS3722_GPIO0_CONTROL_REG 0x08
|
||||
#define AS3722_GPIO1_CONTROL_REG 0x09
|
||||
#define AS3722_GPIO2_CONTROL_REG 0x0A
|
||||
#define AS3722_GPIO3_CONTROL_REG 0x0B
|
||||
#define AS3722_GPIO4_CONTROL_REG 0x0C
|
||||
#define AS3722_GPIO5_CONTROL_REG 0x0D
|
||||
#define AS3722_GPIO6_CONTROL_REG 0x0E
|
||||
#define AS3722_GPIO7_CONTROL_REG 0x0F
|
||||
#define AS3722_LDO0_VOLTAGE_REG 0x10
|
||||
#define AS3722_LDO1_VOLTAGE_REG 0x11
|
||||
#define AS3722_LDO2_VOLTAGE_REG 0x12
|
||||
#define AS3722_LDO3_VOLTAGE_REG 0x13
|
||||
#define AS3722_LDO4_VOLTAGE_REG 0x14
|
||||
#define AS3722_LDO5_VOLTAGE_REG 0x15
|
||||
#define AS3722_LDO6_VOLTAGE_REG 0x16
|
||||
#define AS3722_LDO7_VOLTAGE_REG 0x17
|
||||
#define AS3722_LDO9_VOLTAGE_REG 0x19
|
||||
#define AS3722_LDO10_VOLTAGE_REG 0x1A
|
||||
#define AS3722_LDO11_VOLTAGE_REG 0x1B
|
||||
#define AS3722_GPIO_DEB1_REG 0x1E
|
||||
#define AS3722_GPIO_DEB2_REG 0x1F
|
||||
#define AS3722_GPIO_SIGNAL_OUT_REG 0x20
|
||||
#define AS3722_GPIO_SIGNAL_IN_REG 0x21
|
||||
#define AS3722_REG_SEQU_MOD1_REG 0x22
|
||||
#define AS3722_REG_SEQU_MOD2_REG 0x23
|
||||
#define AS3722_REG_SEQU_MOD3_REG 0x24
|
||||
#define AS3722_SD_PHSW_CTRL_REG 0x27
|
||||
#define AS3722_SD_PHSW_STATUS 0x28
|
||||
#define AS3722_SD0_CONTROL_REG 0x29
|
||||
#define AS3722_SD1_CONTROL_REG 0x2A
|
||||
#define AS3722_SDmph_CONTROL_REG 0x2B
|
||||
#define AS3722_SD23_CONTROL_REG 0x2C
|
||||
#define AS3722_SD4_CONTROL_REG 0x2D
|
||||
#define AS3722_SD5_CONTROL_REG 0x2E
|
||||
#define AS3722_SD6_CONTROL_REG 0x2F
|
||||
#define AS3722_SD_DVM_REG 0x30
|
||||
#define AS3722_RESET_REASON_REG 0x31
|
||||
#define AS3722_BATTERY_VOLTAGE_MONITOR_REG 0x32
|
||||
#define AS3722_STARTUP_CONTROL_REG 0x33
|
||||
#define AS3722_RESET_TIMER_REG 0x34
|
||||
#define AS3722_REFERENCE_CONTROL_REG 0x35
|
||||
#define AS3722_RESET_CONTROL_REG 0x36
|
||||
#define AS3722_OVER_TEMP_CONTROL_REG 0x37
|
||||
#define AS3722_WATCHDOG_CONTROL_REG 0x38
|
||||
#define AS3722_REG_STANDBY_MOD1_REG 0x39
|
||||
#define AS3722_REG_STANDBY_MOD2_REG 0x3A
|
||||
#define AS3722_REG_STANDBY_MOD3_REG 0x3B
|
||||
#define AS3722_ENABLE_CTRL1_REG 0x3C
|
||||
#define AS3722_ENABLE_CTRL2_REG 0x3D
|
||||
#define AS3722_ENABLE_CTRL3_REG 0x3E
|
||||
#define AS3722_ENABLE_CTRL4_REG 0x3F
|
||||
#define AS3722_ENABLE_CTRL5_REG 0x40
|
||||
#define AS3722_PWM_CONTROL_L_REG 0x41
|
||||
#define AS3722_PWM_CONTROL_H_REG 0x42
|
||||
#define AS3722_WATCHDOG_TIMER_REG 0x46
|
||||
#define AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG 0x48
|
||||
#define AS3722_IOVOLTAGE_REG 0x49
|
||||
#define AS3722_BATTERY_VOLTAGE_MONITOR2_REG 0x4A
|
||||
#define AS3722_SD_CONTROL_REG 0x4D
|
||||
#define AS3722_LDOCONTROL0_REG 0x4E
|
||||
#define AS3722_LDOCONTROL1_REG 0x4F
|
||||
#define AS3722_SD0_PROTECT_REG 0x50
|
||||
#define AS3722_SD6_PROTECT_REG 0x51
|
||||
#define AS3722_PWM_VCONTROL1_REG 0x52
|
||||
#define AS3722_PWM_VCONTROL2_REG 0x53
|
||||
#define AS3722_PWM_VCONTROL3_REG 0x54
|
||||
#define AS3722_PWM_VCONTROL4_REG 0x55
|
||||
#define AS3722_BB_CHARGER_REG 0x57
|
||||
#define AS3722_CTRL_SEQU1_REG 0x58
|
||||
#define AS3722_CTRL_SEQU2_REG 0x59
|
||||
#define AS3722_OVCURRENT_REG 0x5A
|
||||
#define AS3722_OVCURRENT_DEB_REG 0x5B
|
||||
#define AS3722_SDLV_DEB_REG 0x5C
|
||||
#define AS3722_OC_PG_CTRL_REG 0x5D
|
||||
#define AS3722_OC_PG_CTRL2_REG 0x5E
|
||||
#define AS3722_CTRL_STATUS 0x5F
|
||||
#define AS3722_RTC_CONTROL_REG 0x60
|
||||
#define AS3722_RTC_SECOND_REG 0x61
|
||||
#define AS3722_RTC_MINUTE_REG 0x62
|
||||
#define AS3722_RTC_HOUR_REG 0x63
|
||||
#define AS3722_RTC_DAY_REG 0x64
|
||||
#define AS3722_RTC_MONTH_REG 0x65
|
||||
#define AS3722_RTC_YEAR_REG 0x66
|
||||
#define AS3722_RTC_ALARM_SECOND_REG 0x67
|
||||
#define AS3722_RTC_ALARM_MINUTE_REG 0x68
|
||||
#define AS3722_RTC_ALARM_HOUR_REG 0x69
|
||||
#define AS3722_RTC_ALARM_DAY_REG 0x6A
|
||||
#define AS3722_RTC_ALARM_MONTH_REG 0x6B
|
||||
#define AS3722_RTC_ALARM_YEAR_REG 0x6C
|
||||
#define AS3722_SRAM_REG 0x6D
|
||||
#define AS3722_RTC_ACCESS_REG 0x6F
|
||||
#define AS3722_RTC_STATUS_REG 0x73
|
||||
#define AS3722_INTERRUPT_MASK1_REG 0x74
|
||||
#define AS3722_INTERRUPT_MASK2_REG 0x75
|
||||
#define AS3722_INTERRUPT_MASK3_REG 0x76
|
||||
#define AS3722_INTERRUPT_MASK4_REG 0x77
|
||||
#define AS3722_INTERRUPT_STATUS1_REG 0x78
|
||||
#define AS3722_INTERRUPT_STATUS2_REG 0x79
|
||||
#define AS3722_INTERRUPT_STATUS3_REG 0x7A
|
||||
#define AS3722_INTERRUPT_STATUS4_REG 0x7B
|
||||
#define AS3722_TEMP_STATUS_REG 0x7D
|
||||
#define AS3722_ADC0_CONTROL_REG 0x80
|
||||
#define AS3722_ADC1_CONTROL_REG 0x81
|
||||
#define AS3722_ADC0_MSB_RESULT_REG 0x82
|
||||
#define AS3722_ADC0_LSB_RESULT_REG 0x83
|
||||
#define AS3722_ADC1_MSB_RESULT_REG 0x84
|
||||
#define AS3722_ADC1_LSB_RESULT_REG 0x85
|
||||
#define AS3722_ADC1_THRESHOLD_HI_MSB_REG 0x86
|
||||
#define AS3722_ADC1_THRESHOLD_HI_LSB_REG 0x87
|
||||
#define AS3722_ADC1_THRESHOLD_LO_MSB_REG 0x88
|
||||
#define AS3722_ADC1_THRESHOLD_LO_LSB_REG 0x89
|
||||
#define AS3722_ADC_CONFIGURATION_REG 0x8A
|
||||
#define AS3722_ASIC_ID1_REG 0x90
|
||||
#define AS3722_ASIC_ID2_REG 0x91
|
||||
#define AS3722_LOCK_REG 0x9E
|
||||
#define AS3722_MAX_REGISTER 0xF4
|
||||
|
||||
#define AS3722_SD0_EXT_ENABLE_MASK 0x03
|
||||
#define AS3722_SD1_EXT_ENABLE_MASK 0x0C
|
||||
#define AS3722_SD2_EXT_ENABLE_MASK 0x30
|
||||
#define AS3722_SD3_EXT_ENABLE_MASK 0xC0
|
||||
#define AS3722_SD4_EXT_ENABLE_MASK 0x03
|
||||
#define AS3722_SD5_EXT_ENABLE_MASK 0x0C
|
||||
#define AS3722_SD6_EXT_ENABLE_MASK 0x30
|
||||
#define AS3722_LDO0_EXT_ENABLE_MASK 0x03
|
||||
#define AS3722_LDO1_EXT_ENABLE_MASK 0x0C
|
||||
#define AS3722_LDO2_EXT_ENABLE_MASK 0x30
|
||||
#define AS3722_LDO3_EXT_ENABLE_MASK 0xC0
|
||||
#define AS3722_LDO4_EXT_ENABLE_MASK 0x03
|
||||
#define AS3722_LDO5_EXT_ENABLE_MASK 0x0C
|
||||
#define AS3722_LDO6_EXT_ENABLE_MASK 0x30
|
||||
#define AS3722_LDO7_EXT_ENABLE_MASK 0xC0
|
||||
#define AS3722_LDO9_EXT_ENABLE_MASK 0x0C
|
||||
#define AS3722_LDO10_EXT_ENABLE_MASK 0x30
|
||||
#define AS3722_LDO11_EXT_ENABLE_MASK 0xC0
|
||||
|
||||
#define AS3722_OVCURRENT_SD0_ALARM_MASK 0x07
|
||||
#define AS3722_OVCURRENT_SD0_ALARM_SHIFT 0x01
|
||||
#define AS3722_OVCURRENT_SD0_TRIP_MASK 0x18
|
||||
#define AS3722_OVCURRENT_SD0_TRIP_SHIFT 0x03
|
||||
#define AS3722_OVCURRENT_SD1_TRIP_MASK 0x60
|
||||
#define AS3722_OVCURRENT_SD1_TRIP_SHIFT 0x05
|
||||
|
||||
#define AS3722_OVCURRENT_SD6_ALARM_MASK 0x07
|
||||
#define AS3722_OVCURRENT_SD6_ALARM_SHIFT 0x01
|
||||
#define AS3722_OVCURRENT_SD6_TRIP_MASK 0x18
|
||||
#define AS3722_OVCURRENT_SD6_TRIP_SHIFT 0x03
|
||||
|
||||
/* AS3722 register bits and bit masks */
|
||||
#define AS3722_LDO_ILIMIT_MASK BIT(7)
|
||||
#define AS3722_LDO_ILIMIT_BIT BIT(7)
|
||||
#define AS3722_LDO0_VSEL_MASK 0x1F
|
||||
#define AS3722_LDO0_VSEL_MIN 0x01
|
||||
#define AS3722_LDO0_VSEL_MAX 0x12
|
||||
#define AS3722_LDO0_NUM_VOLT 0x12
|
||||
#define AS3722_LDO3_VSEL_MASK 0x3F
|
||||
#define AS3722_LDO3_VSEL_MIN 0x01
|
||||
#define AS3722_LDO3_VSEL_MAX 0x2D
|
||||
#define AS3722_LDO3_NUM_VOLT 0x2D
|
||||
#define AS3722_LDO_VSEL_MASK 0x7F
|
||||
#define AS3722_LDO_VSEL_MIN 0x01
|
||||
#define AS3722_LDO_VSEL_MAX 0x7F
|
||||
#define AS3722_LDO_VSEL_DNU_MIN 0x25
|
||||
#define AS3722_LDO_VSEL_DNU_MAX 0x3F
|
||||
#define AS3722_LDO_NUM_VOLT 0x80
|
||||
|
||||
#define AS3722_LDO0_CTRL BIT(0)
|
||||
#define AS3722_LDO1_CTRL BIT(1)
|
||||
#define AS3722_LDO2_CTRL BIT(2)
|
||||
#define AS3722_LDO3_CTRL BIT(3)
|
||||
#define AS3722_LDO4_CTRL BIT(4)
|
||||
#define AS3722_LDO5_CTRL BIT(5)
|
||||
#define AS3722_LDO6_CTRL BIT(6)
|
||||
#define AS3722_LDO7_CTRL BIT(7)
|
||||
#define AS3722_LDO9_CTRL BIT(1)
|
||||
#define AS3722_LDO10_CTRL BIT(2)
|
||||
#define AS3722_LDO11_CTRL BIT(3)
|
||||
|
||||
#define AS3722_LDO3_MODE_MASK (3 << 6)
|
||||
#define AS3722_LDO3_MODE_VAL(n) (((n) & 0x3) << 6)
|
||||
#define AS3722_LDO3_MODE_PMOS AS3722_LDO3_MODE_VAL(0)
|
||||
#define AS3722_LDO3_MODE_PMOS_TRACKING AS3722_LDO3_MODE_VAL(1)
|
||||
#define AS3722_LDO3_MODE_NMOS AS3722_LDO3_MODE_VAL(2)
|
||||
#define AS3722_LDO3_MODE_SWITCH AS3722_LDO3_MODE_VAL(3)
|
||||
|
||||
#define AS3722_SD_VSEL_MASK 0x7F
|
||||
#define AS3722_SD0_VSEL_MIN 0x01
|
||||
#define AS3722_SD0_VSEL_MAX 0x5A
|
||||
#define AS3722_SD2_VSEL_MIN 0x01
|
||||
#define AS3722_SD2_VSEL_MAX 0x7F
|
||||
|
||||
#define AS3722_SDn_CTRL(n) BIT(n)
|
||||
|
||||
#define AS3722_SD0_MODE_FAST BIT(4)
|
||||
#define AS3722_SD1_MODE_FAST BIT(4)
|
||||
#define AS3722_SD2_MODE_FAST BIT(2)
|
||||
#define AS3722_SD3_MODE_FAST BIT(6)
|
||||
#define AS3722_SD4_MODE_FAST BIT(2)
|
||||
#define AS3722_SD5_MODE_FAST BIT(2)
|
||||
#define AS3722_SD6_MODE_FAST BIT(4)
|
||||
|
||||
#define AS3722_POWER_OFF BIT(1)
|
||||
|
||||
#define AS3722_INTERRUPT_MASK1_LID BIT(0)
|
||||
#define AS3722_INTERRUPT_MASK1_ACOK BIT(1)
|
||||
#define AS3722_INTERRUPT_MASK1_ENABLE1 BIT(2)
|
||||
#define AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0 BIT(3)
|
||||
#define AS3722_INTERRUPT_MASK1_ONKEY_LONG BIT(4)
|
||||
#define AS3722_INTERRUPT_MASK1_ONKEY BIT(5)
|
||||
#define AS3722_INTERRUPT_MASK1_OVTMP BIT(6)
|
||||
#define AS3722_INTERRUPT_MASK1_LOWBAT BIT(7)
|
||||
|
||||
#define AS3722_INTERRUPT_MASK2_SD0_LV BIT(0)
|
||||
#define AS3722_INTERRUPT_MASK2_SD1_LV BIT(1)
|
||||
#define AS3722_INTERRUPT_MASK2_SD2345_LV BIT(2)
|
||||
#define AS3722_INTERRUPT_MASK2_PWM1_OV_PROT BIT(3)
|
||||
#define AS3722_INTERRUPT_MASK2_PWM2_OV_PROT BIT(4)
|
||||
#define AS3722_INTERRUPT_MASK2_ENABLE2 BIT(5)
|
||||
#define AS3722_INTERRUPT_MASK2_SD6_LV BIT(6)
|
||||
#define AS3722_INTERRUPT_MASK2_RTC_REP BIT(7)
|
||||
|
||||
#define AS3722_INTERRUPT_MASK3_RTC_ALARM BIT(0)
|
||||
#define AS3722_INTERRUPT_MASK3_GPIO1 BIT(1)
|
||||
#define AS3722_INTERRUPT_MASK3_GPIO2 BIT(2)
|
||||
#define AS3722_INTERRUPT_MASK3_GPIO3 BIT(3)
|
||||
#define AS3722_INTERRUPT_MASK3_GPIO4 BIT(4)
|
||||
#define AS3722_INTERRUPT_MASK3_GPIO5 BIT(5)
|
||||
#define AS3722_INTERRUPT_MASK3_WATCHDOG BIT(6)
|
||||
#define AS3722_INTERRUPT_MASK3_ENABLE3 BIT(7)
|
||||
|
||||
#define AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN BIT(0)
|
||||
#define AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN BIT(1)
|
||||
#define AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN BIT(2)
|
||||
#define AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM BIT(3)
|
||||
#define AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM BIT(4)
|
||||
#define AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM BIT(5)
|
||||
#define AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6 BIT(6)
|
||||
#define AS3722_INTERRUPT_MASK4_ADC BIT(7)
|
||||
|
||||
#define AS3722_ADC1_INTERVAL_TIME BIT(0)
|
||||
#define AS3722_ADC1_INT_MODE_ON BIT(1)
|
||||
#define AS3722_ADC_BUF_ON BIT(2)
|
||||
#define AS3722_ADC1_LOW_VOLTAGE_RANGE BIT(5)
|
||||
#define AS3722_ADC1_INTEVAL_SCAN BIT(6)
|
||||
#define AS3722_ADC1_INT_MASK BIT(7)
|
||||
|
||||
#define AS3722_ADC_MSB_VAL_MASK 0x7F
|
||||
#define AS3722_ADC_LSB_VAL_MASK 0x07
|
||||
|
||||
#define AS3722_ADC0_CONV_START BIT(7)
|
||||
#define AS3722_ADC0_CONV_NOTREADY BIT(7)
|
||||
#define AS3722_ADC0_SOURCE_SELECT_MASK 0x1F
|
||||
|
||||
#define AS3722_ADC1_CONV_START BIT(7)
|
||||
#define AS3722_ADC1_CONV_NOTREADY BIT(7)
|
||||
#define AS3722_ADC1_SOURCE_SELECT_MASK 0x1F
|
||||
|
||||
/* GPIO modes */
|
||||
#define AS3722_GPIO_MODE_MASK 0x07
|
||||
#define AS3722_GPIO_MODE_INPUT 0x00
|
||||
#define AS3722_GPIO_MODE_OUTPUT_VDDH 0x01
|
||||
#define AS3722_GPIO_MODE_IO_OPEN_DRAIN 0x02
|
||||
#define AS3722_GPIO_MODE_ADC_IN 0x03
|
||||
#define AS3722_GPIO_MODE_INPUT_PULL_UP 0x04
|
||||
#define AS3722_GPIO_MODE_INPUT_PULL_DOWN 0x05
|
||||
#define AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP 0x06
|
||||
#define AS3722_GPIO_MODE_OUTPUT_VDDL 0x07
|
||||
#define AS3722_GPIO_MODE_VAL(n) ((n) & AS3722_GPIO_MODE_MASK)
|
||||
|
||||
#define AS3722_GPIO_INV BIT(7)
|
||||
#define AS3722_GPIO_IOSF_MASK 0x78
|
||||
#define AS3722_GPIO_IOSF_VAL(n) (((n) & 0xF) << 3)
|
||||
#define AS3722_GPIO_IOSF_NORMAL AS3722_GPIO_IOSF_VAL(0)
|
||||
#define AS3722_GPIO_IOSF_INTERRUPT_OUT AS3722_GPIO_IOSF_VAL(1)
|
||||
#define AS3722_GPIO_IOSF_VSUP_LOW_OUT AS3722_GPIO_IOSF_VAL(2)
|
||||
#define AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN AS3722_GPIO_IOSF_VAL(3)
|
||||
#define AS3722_GPIO_IOSF_ISINK_PWM_IN AS3722_GPIO_IOSF_VAL(4)
|
||||
#define AS3722_GPIO_IOSF_VOLTAGE_STBY AS3722_GPIO_IOSF_VAL(5)
|
||||
#define AS3722_GPIO_IOSF_PWR_GOOD_OUT AS3722_GPIO_IOSF_VAL(7)
|
||||
#define AS3722_GPIO_IOSF_Q32K_OUT AS3722_GPIO_IOSF_VAL(8)
|
||||
#define AS3722_GPIO_IOSF_WATCHDOG_IN AS3722_GPIO_IOSF_VAL(9)
|
||||
#define AS3722_GPIO_IOSF_SOFT_RESET_IN AS3722_GPIO_IOSF_VAL(11)
|
||||
#define AS3722_GPIO_IOSF_PWM_OUT AS3722_GPIO_IOSF_VAL(12)
|
||||
#define AS3722_GPIO_IOSF_VSUP_LOW_DEB_OUT AS3722_GPIO_IOSF_VAL(13)
|
||||
#define AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW AS3722_GPIO_IOSF_VAL(14)
|
||||
|
||||
#define AS3722_GPIOn_SIGNAL(n) BIT(n)
|
||||
#define AS3722_GPIOn_CONTROL_REG(n) (AS3722_GPIO0_CONTROL_REG + n)
|
||||
#define AS3722_I2C_PULL_UP BIT(4)
|
||||
#define AS3722_INT_PULL_UP BIT(5)
|
||||
|
||||
#define AS3722_RTC_REP_WAKEUP_EN BIT(0)
|
||||
#define AS3722_RTC_ALARM_WAKEUP_EN BIT(1)
|
||||
#define AS3722_RTC_ON BIT(2)
|
||||
#define AS3722_RTC_IRQMODE BIT(3)
|
||||
#define AS3722_RTC_CLK32K_OUT_EN BIT(5)
|
||||
|
||||
#define AS3722_WATCHDOG_TIMER_MAX 0x7F
|
||||
#define AS3722_WATCHDOG_ON BIT(0)
|
||||
#define AS3722_WATCHDOG_SW_SIG BIT(0)
|
||||
|
||||
#define AS3722_EXT_CONTROL_ENABLE1 0x1
|
||||
#define AS3722_EXT_CONTROL_ENABLE2 0x2
|
||||
#define AS3722_EXT_CONTROL_ENABLE3 0x3
|
||||
|
||||
/* Interrupt IDs */
|
||||
enum as3722_irq {
|
||||
AS3722_IRQ_LID,
|
||||
AS3722_IRQ_ACOK,
|
||||
AS3722_IRQ_ENABLE1,
|
||||
AS3722_IRQ_OCCUR_ALARM_SD0,
|
||||
AS3722_IRQ_ONKEY_LONG_PRESS,
|
||||
AS3722_IRQ_ONKEY,
|
||||
AS3722_IRQ_OVTMP,
|
||||
AS3722_IRQ_LOWBAT,
|
||||
AS3722_IRQ_SD0_LV,
|
||||
AS3722_IRQ_SD1_LV,
|
||||
AS3722_IRQ_SD2_LV,
|
||||
AS3722_IRQ_PWM1_OV_PROT,
|
||||
AS3722_IRQ_PWM2_OV_PROT,
|
||||
AS3722_IRQ_ENABLE2,
|
||||
AS3722_IRQ_SD6_LV,
|
||||
AS3722_IRQ_RTC_REP,
|
||||
AS3722_IRQ_RTC_ALARM,
|
||||
AS3722_IRQ_GPIO1,
|
||||
AS3722_IRQ_GPIO2,
|
||||
AS3722_IRQ_GPIO3,
|
||||
AS3722_IRQ_GPIO4,
|
||||
AS3722_IRQ_GPIO5,
|
||||
AS3722_IRQ_WATCHDOG,
|
||||
AS3722_IRQ_ENABLE3,
|
||||
AS3722_IRQ_TEMP_SD0_SHUTDOWN,
|
||||
AS3722_IRQ_TEMP_SD1_SHUTDOWN,
|
||||
AS3722_IRQ_TEMP_SD2_SHUTDOWN,
|
||||
AS3722_IRQ_TEMP_SD0_ALARM,
|
||||
AS3722_IRQ_TEMP_SD1_ALARM,
|
||||
AS3722_IRQ_TEMP_SD6_ALARM,
|
||||
AS3722_IRQ_OCCUR_ALARM_SD6,
|
||||
AS3722_IRQ_ADC,
|
||||
AS3722_IRQ_MAX,
|
||||
};
|
||||
|
||||
struct as3722 {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
int chip_irq;
|
||||
unsigned long irq_flags;
|
||||
bool en_intern_int_pullup;
|
||||
bool en_intern_i2c_pullup;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
};
|
||||
|
||||
static inline int as3722_read(struct as3722 *as3722, u32 reg, u32 *dest)
|
||||
{
|
||||
return regmap_read(as3722->regmap, reg, dest);
|
||||
}
|
||||
|
||||
static inline int as3722_write(struct as3722 *as3722, u32 reg, u32 value)
|
||||
{
|
||||
return regmap_write(as3722->regmap, reg, value);
|
||||
}
|
||||
|
||||
static inline int as3722_block_read(struct as3722 *as3722, u32 reg,
|
||||
int count, u8 *buf)
|
||||
{
|
||||
return regmap_bulk_read(as3722->regmap, reg, buf, count);
|
||||
}
|
||||
|
||||
static inline int as3722_block_write(struct as3722 *as3722, u32 reg,
|
||||
int count, u8 *data)
|
||||
{
|
||||
return regmap_bulk_write(as3722->regmap, reg, data, count);
|
||||
}
|
||||
|
||||
static inline int as3722_update_bits(struct as3722 *as3722, u32 reg,
|
||||
u32 mask, u8 val)
|
||||
{
|
||||
return regmap_update_bits(as3722->regmap, reg, mask, val);
|
||||
}
|
||||
|
||||
static inline int as3722_irq_get_virq(struct as3722 *as3722, int irq)
|
||||
{
|
||||
return regmap_irq_get_virq(as3722->irq_data, irq);
|
||||
}
|
||||
#endif /* __LINUX_MFD_AS3722_H__ */
|
||||
Loading…
Reference in New Issue
Block a user