ARM: tegra30: cpuidle: add powered-down state for CPU0
This is a power gating idle mode. It support power gating vdd_cpu rail after all cpu cores in "powered-down" status. For Tegra30, the CPU0 can enter this state only when all secondary CPU is offline. We need to take care and make sure whole secondary CPUs were offline and checking the CPU power gate status. After that, the CPU0 can go into "powered-down" state safely. Then shut off the CPU rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Base on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Joseph Lo
Stephen Warren
parent
01459c69dd
commit
d552920a02
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@ -32,6 +32,7 @@
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#include "pm.h"
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#include "sleep.h"
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#include "tegra_cpu_car.h"
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#ifdef CONFIG_PM_SLEEP
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static int tegra30_idle_lp2(struct cpuidle_device *dev,
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@ -67,6 +68,31 @@ static struct cpuidle_driver tegra_idle_driver = {
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static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
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#ifdef CONFIG_PM_SLEEP
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static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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struct cpuidle_state *state = &drv->states[index];
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u32 cpu_on_time = state->exit_latency;
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u32 cpu_off_time = state->target_residency - state->exit_latency;
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/* All CPUs entering LP2 is not working.
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* Don't let CPU0 enter LP2 when any secondary CPU is online.
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*/
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if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
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cpu_do_idle();
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return false;
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}
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
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tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
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return true;
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}
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#ifdef CONFIG_SMP
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static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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@ -101,16 +127,22 @@ static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
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{
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u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
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bool entered_lp2 = false;
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bool last_cpu;
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local_fiq_disable();
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tegra_set_cpu_in_lp2(cpu);
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last_cpu = tegra_set_cpu_in_lp2(cpu);
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cpu_pm_enter();
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if (cpu == 0)
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cpu_do_idle();
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else
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if (cpu == 0) {
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if (last_cpu)
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entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
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index);
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else
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cpu_do_idle();
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} else {
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entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
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}
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cpu_pm_exit();
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tegra_clear_cpu_in_lp2(cpu);
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@ -130,6 +162,10 @@ int __init tegra30_cpuidle_init(void)
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struct cpuidle_device *dev;
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struct cpuidle_driver *drv = &tegra_idle_driver;
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#ifdef CONFIG_PM_SLEEP
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tegra_tear_down_cpu = tegra30_tear_down_cpu;
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#endif
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ret = cpuidle_register_driver(&tegra_idle_driver);
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if (ret) {
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pr_err("CPUidle driver registration failed\n");
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@ -20,13 +20,36 @@
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/cpumask.h>
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#include <linux/delay.h>
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#include <linux/cpu_pm.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <asm/smp_plat.h>
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#include <asm/cacheflush.h>
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#include <asm/suspend.h>
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#include <asm/idmap.h>
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#include <asm/proc-fns.h>
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#include <asm/tlbflush.h>
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#include "iomap.h"
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#include "reset.h"
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#include "flowctrl.h"
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#include "sleep.h"
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#include "tegra_cpu_car.h"
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#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
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#define PMC_CTRL 0x0
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#define PMC_CPUPWRGOOD_TIMER 0xc8
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#define PMC_CPUPWROFF_TIMER 0xcc
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#ifdef CONFIG_PM_SLEEP
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static unsigned int g_diag_reg;
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static DEFINE_SPINLOCK(tegra_lp2_lock);
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static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
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static struct clk *tegra_pclk;
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void (*tegra_tear_down_cpu)(void);
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void save_cpu_arch_register(void)
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{
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@ -42,6 +65,89 @@ void restore_cpu_arch_register(void)
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return;
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}
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static void set_power_timers(unsigned long us_on, unsigned long us_off)
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{
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unsigned long long ticks;
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unsigned long long pclk;
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unsigned long rate;
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static unsigned long tegra_last_pclk;
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if (tegra_pclk == NULL) {
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tegra_pclk = clk_get_sys(NULL, "pclk");
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WARN_ON(IS_ERR(tegra_pclk));
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}
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rate = clk_get_rate(tegra_pclk);
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if (WARN_ON_ONCE(rate <= 0))
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pclk = 100000000;
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else
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pclk = rate;
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if ((rate != tegra_last_pclk)) {
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ticks = (us_on * pclk) + 999999ull;
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do_div(ticks, 1000000);
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writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
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ticks = (us_off * pclk) + 999999ull;
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do_div(ticks, 1000000);
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writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
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wmb();
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}
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tegra_last_pclk = pclk;
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}
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/*
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* restore_cpu_complex
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*
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* restores cpu clock setting, clears flow controller
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*
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* Always called on CPU 0.
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*/
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static void restore_cpu_complex(void)
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{
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int cpu = smp_processor_id();
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BUG_ON(cpu != 0);
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(cpu);
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#endif
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/* Restore the CPU clock settings */
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tegra_cpu_clock_resume();
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flowctrl_cpu_suspend_exit(cpu);
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restore_cpu_arch_register();
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}
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/*
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* suspend_cpu_complex
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*
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* saves pll state for use by restart_plls, prepares flow controller for
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* transition to suspend state
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*
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* Must always be called on cpu 0.
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*/
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static void suspend_cpu_complex(void)
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{
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int cpu = smp_processor_id();
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BUG_ON(cpu != 0);
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(cpu);
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#endif
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/* Save the CPU clock settings */
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tegra_cpu_clock_suspend();
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flowctrl_cpu_suspend_enter(cpu);
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save_cpu_arch_register();
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}
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void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id)
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{
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u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
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@ -71,4 +177,42 @@ bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id)
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spin_unlock(&tegra_lp2_lock);
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return last_cpu;
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}
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static int tegra_sleep_cpu(unsigned long v2p)
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{
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/* Switch to the identity mapping. */
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cpu_switch_mm(idmap_pgd, &init_mm);
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/* Flush the TLB. */
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local_flush_tlb_all();
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tegra_sleep_cpu_finish(v2p);
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/* should never here */
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BUG();
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return 0;
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}
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void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
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{
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u32 mode;
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/* Only the last cpu down does the final suspend steps */
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mode = readl(pmc + PMC_CTRL);
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mode |= TEGRA_POWER_CPU_PWRREQ_OE;
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writel(mode, pmc + PMC_CTRL);
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set_power_timers(cpu_on_time, cpu_off_time);
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cpu_cluster_pm_enter();
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suspend_cpu_complex();
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outer_disable();
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cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
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outer_resume();
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restore_cpu_complex();
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cpu_cluster_pm_exit();
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}
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#endif
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@ -27,4 +27,7 @@ void restore_cpu_arch_register(void);
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void tegra_clear_cpu_in_lp2(int phy_cpu_id);
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bool tegra_set_cpu_in_lp2(int phy_cpu_id);
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void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
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extern void (*tegra_tear_down_cpu)(void);
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#endif /* _MACH_TEGRA_PM_H_ */
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@ -124,4 +124,48 @@ ENTRY(tegra30_sleep_cpu_secondary_finish)
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mov r0, #1 @ never return here
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mov pc, r7
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ENDPROC(tegra30_sleep_cpu_secondary_finish)
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/*
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* tegra30_tear_down_cpu
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*
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* Switches the CPU to enter sleep.
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*/
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ENTRY(tegra30_tear_down_cpu)
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mov32 r6, TEGRA_FLOW_CTRL_BASE
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b tegra30_enter_sleep
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ENDPROC(tegra30_tear_down_cpu)
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/*
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* tegra30_enter_sleep
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*
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* uses flow controller to enter sleep state
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* executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
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* executes from SDRAM with target state is LP2
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* r6 = TEGRA_FLOW_CTRL_BASE
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*/
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tegra30_enter_sleep:
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cpu_id r1
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cpu_to_csr_reg r2, r1
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ldr r0, [r6, r2]
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orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
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orr r0, r0, #FLOW_CTRL_CSR_ENABLE
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str r0, [r6, r2]
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mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
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orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
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cpu_to_halt_reg r2, r1
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str r0, [r6, r2]
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dsb
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ldr r0, [r6, r2] /* memory barrier */
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halted:
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isb
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dsb
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wfi /* CPU should be power gated here */
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/* !!!FIXME!!! Implement halt failure handler */
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b halted
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#endif
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@ -25,6 +25,7 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/cache.h>
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#include <asm/cp15.h>
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#include "iomap.h"
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@ -59,4 +60,45 @@ ENTRY(tegra_disable_clean_inv_dcache)
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ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
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ENDPROC(tegra_disable_clean_inv_dcache)
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/*
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* tegra_sleep_cpu_finish(unsigned long v2p)
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*
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* enters suspend in LP2 by turning off the mmu and jumping to
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* tegra?_tear_down_cpu
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*/
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ENTRY(tegra_sleep_cpu_finish)
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/* Flush and disable the L1 data cache */
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bl tegra_disable_clean_inv_dcache
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mov32 r6, tegra_tear_down_cpu
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ldr r1, [r6]
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add r1, r1, r0
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mov32 r3, tegra_shut_off_mmu
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add r3, r3, r0
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mov r0, r1
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mov pc, r3
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ENDPROC(tegra_sleep_cpu_finish)
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/*
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* tegra_shut_off_mmu
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*
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* r0 = physical address to jump to with mmu off
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*
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* called with VA=PA mapping
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* turns off MMU, icache, dcache and branch prediction
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*/
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.align L1_CACHE_SHIFT
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.pushsection .idmap.text, "ax"
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ENTRY(tegra_shut_off_mmu)
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mrc p15, 0, r3, c1, c0, 0
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movw r2, #CR_I | CR_Z | CR_C | CR_M
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bic r3, r3, r2
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dsb
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mcr p15, 0, r3, c1, c0, 0
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isb
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mov pc, r0
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ENDPROC(tegra_shut_off_mmu)
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.popsection
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#endif
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@ -73,6 +73,7 @@
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.endm
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#else
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void tegra_resume(void);
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int tegra_sleep_cpu_finish(unsigned long);
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#ifdef CONFIG_HOTPLUG_CPU
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void tegra20_hotplug_init(void);
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@ -83,6 +84,7 @@ static inline void tegra30_hotplug_init(void) {}
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#endif
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int tegra30_sleep_cpu_secondary_finish(unsigned long);
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void tegra30_tear_down_cpu(void);
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#endif
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#endif
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