luck/tmp_suning_uos_patched
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

habanalabs: rename functions to improve code readability

Browse Source 
This patch renames four functions in the ASIC-specific functions section,
so it will be easier to differentiate them from the generic kernel
functions with the same name.

This will help in future code reviews, to make sure we don't use the
kernel functions directly.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
This commit is contained in:
Oded Gabbay 2019-05-01 11:47:04 +03:00
parent 3706b47006
commit d9c3aa8038
5 changed files with 38 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/misc/habanalabs/command_buffer.c
View File

@ -13,7 +13,7 @@
static void cb_fini(struct hl_device *hdev, struct hl_cb *cb) static void cb_fini(struct hl_device *hdev, struct hl_cb *cb)
{ {
hdev->asic_funcs->dma_free_coherent(hdev, cb->size, hdev->asic_funcs->asic_dma_free_coherent(hdev, cb->size,
(void *) (uintptr_t) cb->kernel_address, (void *) (uintptr_t) cb->kernel_address,
cb->bus_address); cb->bus_address);
kfree(cb); kfree(cb);
@ -66,10 +66,10 @@ static struct hl_cb *hl_cb_alloc(struct hl_device *hdev, u32 cb_size,
return NULL; return NULL;
if (ctx_id == HL_KERNEL_ASID_ID) if (ctx_id == HL_KERNEL_ASID_ID)
p = hdev->asic_funcs->dma_alloc_coherent(hdev, cb_size, p = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, cb_size,
&cb->bus_address, GFP_ATOMIC); &cb->bus_address, GFP_ATOMIC);
else else
p = hdev->asic_funcs->dma_alloc_coherent(hdev, cb_size, p = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, cb_size,
&cb->bus_address, &cb->bus_address,
GFP_USER | __GFP_ZERO); GFP_USER | __GFP_ZERO);
if (!p) { if (!p) {

28
drivers/misc/habanalabs/goya/goya.c
View File

@ -646,7 +646,7 @@ static int goya_sw_init(struct hl_device *hdev)
} }
hdev->cpu_accessible_dma_mem = hdev->cpu_accessible_dma_mem =
hdev->asic_funcs->dma_alloc_coherent(hdev, hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
HL_CPU_ACCESSIBLE_MEM_SIZE, HL_CPU_ACCESSIBLE_MEM_SIZE,
&hdev->cpu_accessible_dma_address, &hdev->cpu_accessible_dma_address,
GFP_KERNEL | __GFP_ZERO); GFP_KERNEL | __GFP_ZERO);
@ -681,7 +681,8 @@ static int goya_sw_init(struct hl_device *hdev)
free_cpu_pq_pool: free_cpu_pq_pool:
gen_pool_destroy(hdev->cpu_accessible_dma_pool); gen_pool_destroy(hdev->cpu_accessible_dma_pool);
free_cpu_pq_dma_mem: free_cpu_pq_dma_mem:
hdev->asic_funcs->dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->asic_funcs->asic_dma_free_coherent(hdev,
HL_CPU_ACCESSIBLE_MEM_SIZE,
hdev->cpu_accessible_dma_mem, hdev->cpu_accessible_dma_mem,
hdev->cpu_accessible_dma_address); hdev->cpu_accessible_dma_address);
free_dma_pool: free_dma_pool:
@ -704,7 +705,8 @@ static int goya_sw_fini(struct hl_device *hdev)
gen_pool_destroy(hdev->cpu_accessible_dma_pool); gen_pool_destroy(hdev->cpu_accessible_dma_pool);
hdev->asic_funcs->dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->asic_funcs->asic_dma_free_coherent(hdev,
HL_CPU_ACCESSIBLE_MEM_SIZE,
hdev->cpu_accessible_dma_mem, hdev->cpu_accessible_dma_mem,
hdev->cpu_accessible_dma_address); hdev->cpu_accessible_dma_address);
@ -2818,7 +2820,7 @@ static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
return -EBUSY; return -EBUSY;
} }
fence_ptr = hdev->asic_funcs->dma_pool_zalloc(hdev, 4, GFP_KERNEL, fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
&fence_dma_addr); &fence_dma_addr);
if (!fence_ptr) { if (!fence_ptr) {
dev_err(hdev->dev, dev_err(hdev->dev,
@ -2867,7 +2869,7 @@ static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
} }
free_fence_ptr: free_fence_ptr:
hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr, hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
fence_dma_addr); fence_dma_addr);
goya_qman0_set_security(hdev, false); goya_qman0_set_security(hdev, false);
@ -2901,7 +2903,7 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
fence_val = GOYA_QMAN0_FENCE_VAL; fence_val = GOYA_QMAN0_FENCE_VAL;
fence_ptr = hdev->asic_funcs->dma_pool_zalloc(hdev, 4, GFP_KERNEL, fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
&fence_dma_addr); &fence_dma_addr);
if (!fence_ptr) { if (!fence_ptr) {
dev_err(hdev->dev, dev_err(hdev->dev,
@ -2911,7 +2913,7 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
*fence_ptr = 0; *fence_ptr = 0;
fence_pkt = hdev->asic_funcs->dma_pool_zalloc(hdev, fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev,
sizeof(struct packet_msg_prot), sizeof(struct packet_msg_prot),
GFP_KERNEL, &pkt_dma_addr); GFP_KERNEL, &pkt_dma_addr);
if (!fence_pkt) { if (!fence_pkt) {
@ -2955,10 +2957,10 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
} }
free_pkt: free_pkt:
hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_pkt, hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt,
pkt_dma_addr); pkt_dma_addr);
free_fence_ptr: free_fence_ptr:
hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr, hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
fence_dma_addr); fence_dma_addr);
return rc; return rc;
} }
@ -4755,12 +4757,12 @@ static const struct hl_asic_funcs goya_funcs = {
.cb_mmap = goya_cb_mmap, .cb_mmap = goya_cb_mmap,
.ring_doorbell = goya_ring_doorbell, .ring_doorbell = goya_ring_doorbell,
.flush_pq_write = goya_flush_pq_write, .flush_pq_write = goya_flush_pq_write,
.dma_alloc_coherent = goya_dma_alloc_coherent, .asic_dma_alloc_coherent = goya_dma_alloc_coherent,
.dma_free_coherent = goya_dma_free_coherent, .asic_dma_free_coherent = goya_dma_free_coherent,
.get_int_queue_base = goya_get_int_queue_base, .get_int_queue_base = goya_get_int_queue_base,
.test_queues = goya_test_queues, .test_queues = goya_test_queues,
.dma_pool_zalloc = goya_dma_pool_zalloc, .asic_dma_pool_zalloc = goya_dma_pool_zalloc,
.dma_pool_free = goya_dma_pool_free, .asic_dma_pool_free = goya_dma_pool_free,
.cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc, .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
.cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free, .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
.hl_dma_unmap_sg = goya_dma_unmap_sg, .hl_dma_unmap_sg = goya_dma_unmap_sg,

30
drivers/misc/habanalabs/habanalabs.h
View File

@ -453,19 +453,19 @@ enum hl_pll_frequency {
* @cb_mmap: maps a CB. * @cb_mmap: maps a CB.
* @ring_doorbell: increment PI on a given QMAN. * @ring_doorbell: increment PI on a given QMAN.
* @flush_pq_write: flush PQ entry write if necessary, WARN if flushing failed. * @flush_pq_write: flush PQ entry write if necessary, WARN if flushing failed.
* @dma_alloc_coherent: Allocate coherent DMA memory by calling * @asic_dma_alloc_coherent: Allocate coherent DMA memory by calling
* dma_alloc_coherent(). This is ASIC function because its * dma_alloc_coherent(). This is ASIC function because
* implementation is not trivial when the driver is loaded * its implementation is not trivial when the driver
* in simulation mode (not upstreamed). * is loaded in simulation mode (not upstreamed).
* @dma_free_coherent: Free coherent DMA memory by calling dma_free_coherent(). * @asic_dma_free_coherent: Free coherent DMA memory by calling
* This is ASIC function because its implementation is not * dma_free_coherent(). This is ASIC function because
* trivial when the driver is loaded in simulation mode * its implementation is not trivial when the driver
* (not upstreamed). * is loaded in simulation mode (not upstreamed).
* @get_int_queue_base: get the internal queue base address. * @get_int_queue_base: get the internal queue base address.
* @test_queues: run simple test on all queues for sanity check. * @test_queues: run simple test on all queues for sanity check.
* @dma_pool_zalloc: small DMA allocation of coherent memory from DMA pool. * @asic_dma_pool_zalloc: small DMA allocation of coherent memory from DMA pool.
* size of allocation is HL_DMA_POOL_BLK_SIZE. * size of allocation is HL_DMA_POOL_BLK_SIZE.
* @dma_pool_free: free small DMA allocation from pool. * @asic_dma_pool_free: free small DMA allocation from pool.
* @cpu_accessible_dma_pool_alloc: allocate CPU PQ packet from DMA pool. * @cpu_accessible_dma_pool_alloc: allocate CPU PQ packet from DMA pool.
* @cpu_accessible_dma_pool_free: free CPU PQ packet from DMA pool. * @cpu_accessible_dma_pool_free: free CPU PQ packet from DMA pool.
* @hl_dma_unmap_sg: DMA unmap scatter-gather list. * @hl_dma_unmap_sg: DMA unmap scatter-gather list.
@ -521,16 +521,16 @@ struct hl_asic_funcs {
u64 kaddress, phys_addr_t paddress, u32 size); u64 kaddress, phys_addr_t paddress, u32 size);
void (*ring_doorbell)(struct hl_device *hdev, u32 hw_queue_id, u32 pi); void (*ring_doorbell)(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
void (*flush_pq_write)(struct hl_device *hdev, u64 *pq, u64 exp_val); void (*flush_pq_write)(struct hl_device *hdev, u64 *pq, u64 exp_val);
void* (*dma_alloc_coherent)(struct hl_device *hdev, size_t size, void* (*asic_dma_alloc_coherent)(struct hl_device *hdev, size_t size,
dma_addr_t *dma_handle, gfp_t flag); dma_addr_t *dma_handle, gfp_t flag);
void (*dma_free_coherent)(struct hl_device *hdev, size_t size, void (*asic_dma_free_coherent)(struct hl_device *hdev, size_t size,
void *cpu_addr, dma_addr_t dma_handle); void *cpu_addr, dma_addr_t dma_handle);
void* (*get_int_queue_base)(struct hl_device *hdev, u32 queue_id, void* (*get_int_queue_base)(struct hl_device *hdev, u32 queue_id,
dma_addr_t *dma_handle, u16 *queue_len); dma_addr_t *dma_handle, u16 *queue_len);
int (*test_queues)(struct hl_device *hdev); int (*test_queues)(struct hl_device *hdev);
void* (*dma_pool_zalloc)(struct hl_device *hdev, size_t size, void* (*asic_dma_pool_zalloc)(struct hl_device *hdev, size_t size,
gfp_t mem_flags, dma_addr_t *dma_handle); gfp_t mem_flags, dma_addr_t *dma_handle);
void (*dma_pool_free)(struct hl_device *hdev, void *vaddr, void (*asic_dma_pool_free)(struct hl_device *hdev, void *vaddr,
dma_addr_t dma_addr); dma_addr_t dma_addr);
void* (*cpu_accessible_dma_pool_alloc)(struct hl_device *hdev, void* (*cpu_accessible_dma_pool_alloc)(struct hl_device *hdev,
size_t size, dma_addr_t *dma_handle); size_t size, dma_addr_t *dma_handle);

6
drivers/misc/habanalabs/hw_queue.c
View File

@ -425,7 +425,7 @@ static int ext_and_cpu_hw_queue_init(struct hl_device *hdev,
HL_QUEUE_SIZE_IN_BYTES, HL_QUEUE_SIZE_IN_BYTES,
&q->bus_address); &q->bus_address);
else else
p = hdev->asic_funcs->dma_alloc_coherent(hdev, p = hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
HL_QUEUE_SIZE_IN_BYTES, HL_QUEUE_SIZE_IN_BYTES,
&q->bus_address, &q->bus_address,
GFP_KERNEL | __GFP_ZERO); GFP_KERNEL | __GFP_ZERO);
@ -457,7 +457,7 @@ static int ext_and_cpu_hw_queue_init(struct hl_device *hdev,
HL_QUEUE_SIZE_IN_BYTES, HL_QUEUE_SIZE_IN_BYTES,
(void *) (uintptr_t) q->kernel_address); (void *) (uintptr_t) q->kernel_address);
else else
hdev->asic_funcs->dma_free_coherent(hdev, hdev->asic_funcs->asic_dma_free_coherent(hdev,
HL_QUEUE_SIZE_IN_BYTES, HL_QUEUE_SIZE_IN_BYTES,
(void *) (uintptr_t) q->kernel_address, (void *) (uintptr_t) q->kernel_address,
q->bus_address); q->bus_address);
@ -587,7 +587,7 @@ static void hw_queue_fini(struct hl_device *hdev, struct hl_hw_queue *q)
HL_QUEUE_SIZE_IN_BYTES, HL_QUEUE_SIZE_IN_BYTES,
(void *) (uintptr_t) q->kernel_address); (void *) (uintptr_t) q->kernel_address);
else else
hdev->asic_funcs->dma_free_coherent(hdev, hdev->asic_funcs->asic_dma_free_coherent(hdev,
HL_QUEUE_SIZE_IN_BYTES, HL_QUEUE_SIZE_IN_BYTES,
(void *) (uintptr_t) q->kernel_address, (void *) (uintptr_t) q->kernel_address,
q->bus_address); q->bus_address);

4
drivers/misc/habanalabs/irq.c
View File

@ -222,7 +222,7 @@ int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id)
BUILD_BUG_ON(HL_CQ_SIZE_IN_BYTES > HL_PAGE_SIZE); BUILD_BUG_ON(HL_CQ_SIZE_IN_BYTES > HL_PAGE_SIZE);
p = hdev->asic_funcs->dma_alloc_coherent(hdev, HL_CQ_SIZE_IN_BYTES, p = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, HL_CQ_SIZE_IN_BYTES,
&q->bus_address, GFP_KERNEL | __GFP_ZERO); &q->bus_address, GFP_KERNEL | __GFP_ZERO);
if (!p) if (!p)
return -ENOMEM; return -ENOMEM;
@ -248,7 +248,7 @@ int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id)
*/ */
void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q) void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q)
{ {
hdev->asic_funcs->dma_free_coherent(hdev, HL_CQ_SIZE_IN_BYTES, hdev->asic_funcs->asic_dma_free_coherent(hdev, HL_CQ_SIZE_IN_BYTES,
(void *) (uintptr_t) q->kernel_address, q->bus_address); (void *) (uintptr_t) q->kernel_address, q->bus_address);
} }