luck/tmp_suning_uos_patched
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

clk: meson: axg: spread spectrum is on mpll2

Browse Source 
After testing, it appears that the SSEN bit controls the spread
spectrum function on MPLL2, not MPLL0.

Fixes: 78b4af312f ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Jerome Brunet 2019-05-13 14:31:11 +02:00
parent 8925dbd03b
commit dc4e62d373
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/clk/meson/axg.c
View File

@ -469,11 +469,6 @@ static struct clk_regmap axg_mpll0_div = {
.shift = 16,
.width = 9,
},
.ssen = {
.reg_off = HHI_MPLL_CNTL,
.shift = 25,
.width = 1,
},
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift = 0,
@ -568,6 +563,11 @@ static struct clk_regmap axg_mpll2_div = {
.shift = 16,
.width = 9,
},
.ssen = {
.reg_off = HHI_MPLL_CNTL,
.shift = 25,
.width = 1,
},
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift = 2,