clk: tegra: Changes for v4.4-rc1
This contains a patch that allows the DFLL to use clock rates higher than 2^31-1 Hz by using the ->determine_rate() operation instead of the ->round_rate() operation. Other than that there's a couple of cleanups in preparation for Tegra210 support. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJWJjSRAAoJEN0jrNd/PrOh9vEP/0fhpVjrPPhnTSAMbdIA6kkB 5TThz2ja2AyoFTXyPS1SO77LPbk55LXuuTxcEiYDK5kokK8QcbIcYSEWQcbUsYEo 3gPiFVegmOcp1IZgJhU9RAQmqfWuQJuNYcWpHHFsz2otyVqlGWIyX6n1UzT47nmw zYvTFGmke28LMt9GnOR1X8ma3rnefYQw+ZcxSinzXhansKAfXtXpr0ixfCpSlqZl 7f+mSs5GW8QgJdm5ml4Y7BIk7Fopkr9ic4Js70OxbFmqKu9EU2p4bExFXmdfMQbU gq/jd/ZJQjlbNAluGBb7vjzHKN9InjzkxkNHyode8vix411z5Xx2TelYUbayNMh+ fCyn7Sr4tG2u4OZapH1zYV3YgIW08zQSpdkuq/J/8RuAN35WDYQMld4V7jHt7l0p 6Z/yVsM2llFwpmLu5DgeVYRXLt/3ConBwcAEn3EnEpQHXJXa9BBD6D3Uv7ErVAyJ aKN5p8Ix91/rX6JCa2g5tNTRs1arn5TfDQ2nJpGUmN4/SRMVb6L/ezmcPhqrDXVd Cp6xfvRS4TloYxuGbxpmpP+Hwev+GVN0AfEq3jpA7EmOvRLeexnVHhsnIvMbnEqw ucigNua0nWEqF0PechSpIIEp0rcdqD70kqNkTK/fzaWXPlg9GyI7W83JsDFh7PF1 2caoSL9E6jPE5F8L6NMz =4qKy -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.4-rc1 This contains a patch that allows the DFLL to use clock rates higher than 2^31-1 Hz by using the ->determine_rate() operation instead of the ->round_rate() operation. Other than that there's a couple of cleanups in preparation for Tegra210 support.
This commit is contained in:
Michael Turquette
commit
eae14465de
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@ -468,56 +468,6 @@ static unsigned long dfll_scale_dvco_rate(int scale_bits,
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return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX;
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}
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/*
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* Monitor control
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*/
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/**
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* dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
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* @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield
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* @ref_rate: DFLL reference clock rate
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*
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* Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles
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* per second. Returns the converted value.
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*/
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static u64 dfll_calc_monitored_rate(u32 monitor_data,
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unsigned long ref_rate)
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{
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return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);
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}
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/**
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* dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
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* @td: DFLL instance
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*
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* If the DFLL is enabled, return the last rate reported by the DFLL's
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* internal monitoring hardware. This works in both open-loop and
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* closed-loop mode, and takes the output scaler setting into account.
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* Assumes that the monitor was programmed to monitor frequency before
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* the sample period started. If the driver believes that the DFLL is
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* currently uninitialized or disabled, it will return 0, since
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* otherwise the DFLL monitor data register will return the last
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* measured rate from when the DFLL was active.
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*/
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static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
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{
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u32 v, s;
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u64 pre_scaler_rate, post_scaler_rate;
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if (!dfll_is_running(td))
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return 0;
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v = dfll_readl(td, DFLL_MONITOR_DATA);
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v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
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pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
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s = dfll_readl(td, DFLL_FREQ_REQ);
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s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
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post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);
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return post_scaler_rate;
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}
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/*
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* DFLL mode switching
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*/
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@ -1006,24 +956,25 @@ static unsigned long dfll_clk_recalc_rate(struct clk_hw *hw,
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return td->last_unrounded_rate;
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}
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static long dfll_clk_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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/* Must use determine_rate since it allows for rates exceeding 2^31-1 */
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static int dfll_clk_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *clk_req)
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{
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struct tegra_dfll *td = clk_hw_to_dfll(hw);
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struct dfll_rate_req req;
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int ret;
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ret = dfll_calculate_rate_request(td, &req, rate);
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ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
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if (ret)
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return ret;
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/*
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* Don't return the rounded rate, since it doesn't really matter as
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* Don't set the rounded rate, since it doesn't really matter as
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* the output rate will be voltage controlled anyway, and cpufreq
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* freaks out if any rounding happens.
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*/
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return rate;
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return 0;
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}
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static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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@ -1039,7 +990,7 @@ static const struct clk_ops dfll_clk_ops = {
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.enable = dfll_clk_enable,
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.disable = dfll_clk_disable,
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.recalc_rate = dfll_clk_recalc_rate,
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.round_rate = dfll_clk_round_rate,
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.determine_rate = dfll_clk_determine_rate,
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.set_rate = dfll_clk_set_rate,
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};
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@ -1101,6 +1052,55 @@ static void dfll_unregister_clk(struct tegra_dfll *td)
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*/
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#ifdef CONFIG_DEBUG_FS
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/*
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* Monitor control
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*/
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/**
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* dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
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* @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield
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* @ref_rate: DFLL reference clock rate
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*
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* Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles
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* per second. Returns the converted value.
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*/
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static u64 dfll_calc_monitored_rate(u32 monitor_data,
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unsigned long ref_rate)
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{
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return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);
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}
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/**
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* dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
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* @td: DFLL instance
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*
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* If the DFLL is enabled, return the last rate reported by the DFLL's
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* internal monitoring hardware. This works in both open-loop and
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* closed-loop mode, and takes the output scaler setting into account.
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* Assumes that the monitor was programmed to monitor frequency before
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* the sample period started. If the driver believes that the DFLL is
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* currently uninitialized or disabled, it will return 0, since
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* otherwise the DFLL monitor data register will return the last
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* measured rate from when the DFLL was active.
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*/
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static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
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{
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u32 v, s;
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u64 pre_scaler_rate, post_scaler_rate;
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if (!dfll_is_running(td))
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return 0;
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v = dfll_readl(td, DFLL_MONITOR_DATA);
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v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
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pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
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s = dfll_readl(td, DFLL_FREQ_REQ);
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s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
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post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);
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return post_scaler_rate;
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}
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static int attr_enable_get(void *data, u64 *val)
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{
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@ -125,18 +125,29 @@ static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
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void __init tegra_audio_clk_init(void __iomem *clk_base,
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void __iomem *pmc_base, struct tegra_clk *tegra_clks,
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struct tegra_clk_pll_params *pll_a_params)
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struct tegra_audio_clk_info *audio_info,
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unsigned int num_plls)
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{
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struct clk *clk;
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struct clk **dt_clk;
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int i;
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/* PLLA */
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dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a, tegra_clks);
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if (dt_clk) {
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clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base,
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pmc_base, 0, pll_a_params, NULL);
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*dt_clk = clk;
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if (!audio_info || num_plls < 1) {
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pr_err("No audio data passed to tegra_audio_clk_init\n");
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WARN_ON(1);
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return;
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}
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for (i = 0; i < num_plls; i++) {
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struct tegra_audio_clk_info *info = &audio_info[i];
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dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks);
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if (dt_clk) {
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clk = tegra_clk_register_pll(info->name, info->parent,
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clk_base, pmc_base, 0, info->pll_params,
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NULL);
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*dt_clk = clk;
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}
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}
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/* PLLA_OUT0 */
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@ -933,6 +933,10 @@ static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
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[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
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};
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static struct tegra_audio_clk_info tegra114_audio_plls[] = {
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{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
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};
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static struct clk **clks;
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static unsigned long osc_freq;
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@ -1481,7 +1485,9 @@ static void __init tegra114_clock_init(struct device_node *np)
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tegra114_fixed_clk_init(clk_base);
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tegra114_pll_init(clk_base, pmc_base);
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tegra114_periph_clk_init(clk_base, pmc_base);
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tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
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tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
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tegra114_audio_plls,
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ARRAY_SIZE(tegra114_audio_plls));
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tegra_pmc_clk_init(pmc_base, tegra114_clks);
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tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
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&pll_x_params);
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@ -1417,6 +1417,10 @@ static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
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{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
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};
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static struct tegra_audio_clk_info tegra124_audio_plls[] = {
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{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
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};
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/**
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* tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
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*
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@ -1555,7 +1559,9 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
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tegra_fixed_clk_init(tegra124_clks);
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tegra124_pll_init(clk_base, pmc_base);
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tegra124_periph_clk_init(clk_base, pmc_base);
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tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
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tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
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tegra124_audio_plls,
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ARRAY_SIZE(tegra124_audio_plls));
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tegra_pmc_clk_init(pmc_base, tegra124_clks);
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/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
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@ -1405,6 +1405,10 @@ static const struct of_device_id pmc_match[] __initconst = {
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{},
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};
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static struct tegra_audio_clk_info tegra30_audio_plls[] = {
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{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
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};
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static void __init tegra30_clock_init(struct device_node *np)
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{
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struct device_node *node;
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@ -1442,7 +1446,9 @@ static void __init tegra30_clock_init(struct device_node *np)
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tegra30_pll_init();
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tegra30_super_clk_init();
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tegra30_periph_clk_init();
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tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, &pll_a_params);
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tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
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tegra30_audio_plls,
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ARRAY_SIZE(tegra30_audio_plls));
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tegra_pmc_clk_init(pmc_base, tegra30_clks);
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tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
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@ -157,7 +157,7 @@ struct div_nmp {
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};
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/**
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* struct clk_pll_params - PLL parameters
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* struct tegra_clk_pll_params - PLL parameters
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*
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* @input_min: Minimum input frequency
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* @input_max: Maximum input frequency
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@ -168,9 +168,45 @@ struct div_nmp {
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* @base_reg: PLL base reg offset
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* @misc_reg: PLL misc reg offset
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* @lock_reg: PLL lock reg offset
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* @lock_bit_idx: Bit index for PLL lock status
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* @lock_mask: Bitmask for PLL lock status
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* @lock_enable_bit_idx: Bit index to enable PLL lock
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* @iddq_reg: PLL IDDQ register offset
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* @iddq_bit_idx: Bit index to enable PLL IDDQ
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* @aux_reg: AUX register offset
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* @dyn_ramp_reg: Dynamic ramp control register offset
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* @ext_misc_reg: Miscellaneous control register offsets
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* @pmc_divnm_reg: n, m divider PMC override register offset (PLLM)
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* @pmc_divp_reg: p divider PMC override register offset (PLLM)
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* @flags: PLL flags
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* @stepa_shift: Dynamic ramp step A field shift
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* @stepb_shift: Dynamic ramp step B field shift
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* @lock_delay: Delay in us if PLL lock is not used
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* @max_p: maximum value for the p divider
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* @pdiv_tohw: mapping of p divider to register values
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* @div_nmp: offsets and widths on n, m and p fields
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* @freq_table: array of frequencies supported by PLL
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* @fixed_rate: PLL rate if it is fixed
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*
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* Flags:
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* TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
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* PLL locking. If not set it will use lock_delay value to wait.
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* TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
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* that it is PLLU and invert post divider value.
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* TEGRA_PLLM - PLLM has additional override settings in PMC. This
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* flag indicates that it is PLLM and use override settings.
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* TEGRA_PLL_FIXED - We are not supposed to change output frequency
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* of some plls.
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* TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
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* TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
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* base register.
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* TEGRA_PLL_BYPASS - PLL has bypass bit
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* TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
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*/
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struct tegra_clk_pll_params {
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unsigned long input_min;
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@ -203,49 +239,6 @@ struct tegra_clk_pll_params {
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unsigned long fixed_rate;
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};
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/**
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* struct tegra_clk_pll - Tegra PLL clock
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*
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* @hw: handle between common and hardware-specifix interfaces
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* @clk_base: address of CAR controller
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* @pmc: address of PMC, required to read override bits
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* @freq_table: array of frequencies supported by PLL
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* @params: PLL parameters
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* @flags: PLL flags
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* @fixed_rate: PLL rate if it is fixed
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* @lock: register lock
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*
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* Flags:
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* TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
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* PLL locking. If not set it will use lock_delay value to wait.
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* TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
|
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
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* that it is PLLU and invert post divider value.
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* TEGRA_PLLM - PLLM has additional override settings in PMC. This
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* flag indicates that it is PLLM and use override settings.
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* TEGRA_PLL_FIXED - We are not supposed to change output frequency
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* of some plls.
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* TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
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* TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
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* base register.
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* TEGRA_PLL_BYPASS - PLL has bypass bit
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* TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
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*/
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struct tegra_clk_pll {
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struct clk_hw hw;
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void __iomem *clk_base;
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void __iomem *pmc;
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spinlock_t *lock;
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struct tegra_clk_pll_params *params;
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};
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||||
|
||||
#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
|
||||
|
||||
#define TEGRA_PLL_USE_LOCK BIT(0)
|
||||
#define TEGRA_PLL_HAS_CPCON BIT(1)
|
||||
#define TEGRA_PLL_SET_LFCON BIT(2)
|
||||
|
|
@ -258,6 +251,40 @@ struct tegra_clk_pll {
|
|||
#define TEGRA_PLL_BYPASS BIT(9)
|
||||
#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
|
||||
|
||||
/**
|
||||
* struct tegra_clk_pll - Tegra PLL clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specifix interfaces
|
||||
* @clk_base: address of CAR controller
|
||||
* @pmc: address of PMC, required to read override bits
|
||||
* @lock: register lock
|
||||
* @params: PLL parameters
|
||||
*/
|
||||
struct tegra_clk_pll {
|
||||
struct clk_hw hw;
|
||||
void __iomem *clk_base;
|
||||
void __iomem *pmc;
|
||||
spinlock_t *lock;
|
||||
struct tegra_clk_pll_params *params;
|
||||
};
|
||||
|
||||
#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
|
||||
|
||||
/**
|
||||
* struct tegra_audio_clk_info - Tegra Audio Clk Information
|
||||
*
|
||||
* @name: name for the audio pll
|
||||
* @pll_params: pll_params for audio pll
|
||||
* @clk_id: clk_ids for the audio pll
|
||||
* @parent: name of the parent of the audio pll
|
||||
*/
|
||||
struct tegra_audio_clk_info {
|
||||
char *name;
|
||||
struct tegra_clk_pll_params *pll_params;
|
||||
int clk_id;
|
||||
char *parent;
|
||||
};
|
||||
|
||||
extern const struct clk_ops tegra_clk_pll_ops;
|
||||
extern const struct clk_ops tegra_clk_plle_ops;
|
||||
struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
|
||||
|
|
@ -610,7 +637,8 @@ void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
|
|||
|
||||
void tegra_audio_clk_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *pll_params);
|
||||
struct tegra_audio_clk_info *audio_info,
|
||||
unsigned int num_plls);
|
||||
|
||||
void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks,
|
||||
|
|
|
|||
|
|
@ -78,13 +78,6 @@ static int build_opp_table(const struct cvb_table *d,
|
|||
if (!table->freq || (table->freq > max_freq))
|
||||
break;
|
||||
|
||||
/*
|
||||
* FIXME after clk_round_rate/clk_determine_rate prototypes
|
||||
* have been updated
|
||||
*/
|
||||
if (table->freq & (1<<31))
|
||||
continue;
|
||||
|
||||
dfll_mv = get_cvb_voltage(
|
||||
speedo_value, d->speedo_scale, &table->coefficients);
|
||||
dfll_mv = round_cvb_voltage(dfll_mv, d->voltage_scale, align);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user