ARM: OMAP: Powerdomain: Add OMAP3 powerdomains
Add OMAP3-specific powerdomains. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -98,16 +98,28 @@ static struct pwrdm_dep gfx_sgx_wkdeps[] = {
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{ NULL },
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};
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/*
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* 3430: CM_SLEEPDEP_CAM: MPU
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* 3430ES1: CM_SLEEPDEP_GFX: MPU
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* 3430ES2: CM_SLEEPDEP_SGX: MPU
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*/
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static struct pwrdm_dep cam_gfx_sleepdeps[] = {
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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#include "powerdomains24xx.h"
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#include "powerdomains34xx.h"
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/*
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* OMAP2/3 common powerdomains
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*/
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/* XXX add sleepdeps for this powerdomain : 3430 */
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/*
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* The GFX powerdomain is not present on 3430ES2, but currently we do not
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* have a macro to filter it out at compile-time.
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@ -118,6 +130,7 @@ static struct powerdomain gfx_pwrdm = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
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CHIP_IS_OMAP3430ES1),
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.wkdep_srcs = gfx_sgx_wkdeps,
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.sleepdep_srcs = cam_gfx_sleepdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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@ -154,6 +167,19 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
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&mdm_pwrdm,
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#endif
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#ifdef CONFIG_ARCH_OMAP34XX
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&iva2_pwrdm,
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&mpu_34xx_pwrdm,
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&neon_pwrdm,
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&core_34xx_pwrdm,
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&cam_pwrdm,
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&dss_pwrdm,
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&per_pwrdm,
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&emu_pwrdm,
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&sgx_pwrdm,
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&usbhost_pwrdm,
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#endif
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NULL
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};
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327
arch/arm/mach-omap2/powerdomains34xx.h
Normal file
327
arch/arm/mach-omap2/powerdomains34xx.h
Normal file
@ -0,0 +1,327 @@
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/*
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* OMAP34XX powerdomain definitions
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2008 Nokia Corporation
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*
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* Written by Paul Walmsley
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* Debugging and integration fixes by Jouni Högander
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
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#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
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/*
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* N.B. If powerdomains are added or removed from this file, update
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* the array in mach-omap2/powerdomains.h.
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*/
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#include <mach/powerdomain.h>
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#include "prcm-common.h"
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#include "prm.h"
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#include "prm-regbits-34xx.h"
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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/*
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* 34XX-specific powerdomains, dependencies
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*/
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#ifdef CONFIG_ARCH_OMAP34XX
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/*
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* 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
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* (USBHOST is ES2 only)
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*/
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static struct pwrdm_dep per_usbhost_wkdeps[] = {
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{
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.pwrdm_name = "core_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "iva2_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "wkup_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/*
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* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
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*/
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static struct pwrdm_dep mpu_34xx_wkdeps[] = {
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{
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.pwrdm_name = "core_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "iva2_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "dss_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "per_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/*
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* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
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*/
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static struct pwrdm_dep iva2_wkdeps[] = {
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{
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.pwrdm_name = "core_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "wkup_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "dss_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "per_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
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static struct pwrdm_dep cam_dss_wkdeps[] = {
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{
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.pwrdm_name = "iva2_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "wkup_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430: PM_WKDEP_NEON: MPU */
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static struct pwrdm_dep neon_wkdeps[] = {
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
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/*
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* 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
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* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
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*/
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static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "iva2_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/*
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* Powerdomains
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*/
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static struct powerdomain iva2_pwrdm = {
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.name = "iva2_pwrdm",
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.prcm_offs = OMAP3430_IVA2_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
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.wkdep_srcs = iva2_wkdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 4,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET,
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[1] = PWRSTS_OFF_RET,
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[2] = PWRSTS_OFF_RET,
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[3] = PWRSTS_OFF_RET,
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON,
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[1] = PWRDM_POWER_ON,
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[2] = PWRSTS_OFF_ON,
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[3] = PWRDM_POWER_ON,
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},
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};
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static struct powerdomain mpu_34xx_pwrdm = {
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.name = "mpu_pwrdm",
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.prcm_offs = MPU_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.dep_bit = OMAP3430_EN_MPU_SHIFT,
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.wkdep_srcs = mpu_34xx_wkdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET,
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_ON,
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},
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};
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/* No wkdeps or sleepdeps for 34xx core apparently */
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static struct powerdomain core_34xx_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = CORE_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.dep_bit = OMAP3430_EN_CORE_SHIFT,
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
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[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
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[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
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},
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};
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/* Another case of bit name collisions between several registers: EN_DSS */
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static struct powerdomain dss_pwrdm = {
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.name = "dss_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.prcm_offs = OMAP3430_DSS_MOD,
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.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
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.wkdep_srcs = cam_dss_wkdeps,
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.sleepdep_srcs = dss_per_usbhost_sleepdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain sgx_pwrdm = {
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.name = "sgx_pwrdm",
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.prcm_offs = OMAP3430ES2_SGX_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
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.wkdep_srcs = gfx_sgx_wkdeps,
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.sleepdep_srcs = cam_gfx_sleepdeps,
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/* XXX This is accurate for 3430 SGX, but what about GFX? */
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain cam_pwrdm = {
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.name = "cam_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.prcm_offs = OMAP3430_CAM_MOD,
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.wkdep_srcs = cam_dss_wkdeps,
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.sleepdep_srcs = cam_gfx_sleepdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain per_pwrdm = {
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.name = "per_pwrdm",
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.prcm_offs = OMAP3430_PER_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.dep_bit = OMAP3430_EN_PER_SHIFT,
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.wkdep_srcs = per_usbhost_wkdeps,
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.sleepdep_srcs = dss_per_usbhost_sleepdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain emu_pwrdm = {
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.name = "emu_pwrdm",
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.prcm_offs = OMAP3430_EMU_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct powerdomain neon_pwrdm = {
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.name = "neon_pwrdm",
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.prcm_offs = OMAP3430_NEON_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.wkdep_srcs = neon_wkdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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};
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static struct powerdomain usbhost_pwrdm = {
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.name = "usbhost_pwrdm",
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.prcm_offs = OMAP3430ES2_USBHOST_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
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.wkdep_srcs = per_usbhost_wkdeps,
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.sleepdep_srcs = dss_per_usbhost_sleepdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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#endif /* CONFIG_ARCH_OMAP34XX */
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#endif
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@ -312,7 +312,8 @@
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#define OMAP3430_ST_GPT2 (1 << 3)
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/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
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#define OMAP3430_EN_CORE (1 << 0)
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#define OMAP3430_EN_CORE_SHIFT 0
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#define OMAP3430_EN_CORE_MASK (1 << 0)
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#endif
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@ -68,7 +68,8 @@
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#define OMAP3430_VPINIDLE (1 << 0)
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/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
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#define OMAP3430_EN_PER (1 << 7)
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#define OMAP3430_EN_PER_SHIFT 7
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#define OMAP3430_EN_PER_MASK (1 << 7)
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/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
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#define OMAP3430_MEMORYCHANGE (1 << 3)
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@ -77,7 +78,7 @@
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#define OMAP3430_LOGICSTATEST (1 << 2)
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/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
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#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
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#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
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/*
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* PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
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@ -278,8 +279,10 @@
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#define OMAP3430_EMULATION_MPU_RST (1 << 11)
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/* PM_WKDEP_MPU specific bits */
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#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5)
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#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2)
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#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
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#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
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#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
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#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
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|
||||
/* PM_EVGENCTRL_MPU */
|
||||
#define OMAP3430_OFFLOADMODE_SHIFT 3
|
||||
|
Loading…
Reference in New Issue
Block a user