MIPS: Alchemy: au1200fb: use clk framework
minimal patch to replace direct clock register hackery with clock framework calls. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7472/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -30,6 +30,7 @@
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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@ -330,9 +331,8 @@ struct panel_settings
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uint32 mode_pwmhi;
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uint32 mode_outmask;
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uint32 mode_fifoctrl;
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uint32 mode_toyclksrc;
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uint32 mode_backlight;
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uint32 mode_auxpll;
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uint32 lcdclk;
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#define Xres min_xres
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#define Yres min_yres
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u32 min_xres; /* Minimum horizontal resolution */
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@ -379,9 +379,8 @@ static struct panel_settings known_lcd_panels[] =
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.mode_pwmhi = 0x00000000,
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.mode_outmask = 0x00FFFFFF,
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.mode_fifoctrl = 0x2f2f2f2f,
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.mode_toyclksrc = 0x00000004, /* AUXPLL directly */
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.mode_backlight = 0x00000000,
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.mode_auxpll = 8, /* 96MHz AUXPLL */
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.lcdclk = 96,
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320, 320,
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240, 240,
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},
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@ -407,9 +406,8 @@ static struct panel_settings known_lcd_panels[] =
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.mode_pwmhi = 0x00000000,
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.mode_outmask = 0x00FFFFFF,
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.mode_fifoctrl = 0x2f2f2f2f,
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.mode_toyclksrc = 0x00000004, /* AUXPLL directly */
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.mode_backlight = 0x00000000,
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.mode_auxpll = 8, /* 96MHz AUXPLL */
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.lcdclk = 96,
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640, 480,
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640, 480,
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},
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@ -435,9 +433,8 @@ static struct panel_settings known_lcd_panels[] =
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.mode_pwmhi = 0x00000000,
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.mode_outmask = 0x00FFFFFF,
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.mode_fifoctrl = 0x2f2f2f2f,
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.mode_toyclksrc = 0x00000004, /* AUXPLL directly */
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.mode_backlight = 0x00000000,
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.mode_auxpll = 8, /* 96MHz AUXPLL */
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.lcdclk = 96,
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800, 800,
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600, 600,
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},
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@ -463,9 +460,8 @@ static struct panel_settings known_lcd_panels[] =
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.mode_pwmhi = 0x00000000,
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.mode_outmask = 0x00FFFFFF,
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.mode_fifoctrl = 0x2f2f2f2f,
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.mode_toyclksrc = 0x00000004, /* AUXPLL directly */
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.mode_backlight = 0x00000000,
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.mode_auxpll = 6, /* 72MHz AUXPLL */
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.lcdclk = 72,
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1024, 1024,
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768, 768,
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},
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@ -491,9 +487,8 @@ static struct panel_settings known_lcd_panels[] =
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.mode_pwmhi = 0x00000000,
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.mode_outmask = 0x00FFFFFF,
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.mode_fifoctrl = 0x2f2f2f2f,
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.mode_toyclksrc = 0x00000004, /* AUXPLL directly */
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.mode_backlight = 0x00000000,
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.mode_auxpll = 10, /* 120MHz AUXPLL */
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.lcdclk = 120,
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1280, 1280,
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1024, 1024,
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},
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@ -519,9 +514,8 @@ static struct panel_settings known_lcd_panels[] =
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.mode_pwmhi = 0x03400000, /* SCB 0x0 */
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.mode_outmask = 0x00FFFFFF,
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.mode_fifoctrl = 0x2f2f2f2f,
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.mode_toyclksrc = 0x00000004, /* AUXPLL directly */
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.mode_backlight = 0x00000000,
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.mode_auxpll = 8, /* 96MHz AUXPLL */
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.lcdclk = 96,
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1024, 1024,
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768, 768,
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},
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@ -550,9 +544,8 @@ static struct panel_settings known_lcd_panels[] =
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.mode_pwmhi = 0x03400000,
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.mode_outmask = 0x00fcfcfc,
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.mode_fifoctrl = 0x2f2f2f2f,
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.mode_toyclksrc = 0x00000004, /* AUXPLL directly */
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.mode_backlight = 0x00000000,
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.mode_auxpll = 8, /* 96MHz AUXPLL */
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.lcdclk = 96,
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640, 480,
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640, 480,
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},
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@ -581,9 +574,8 @@ static struct panel_settings known_lcd_panels[] =
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.mode_pwmhi = 0x03400000,
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.mode_outmask = 0x00fcfcfc,
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.mode_fifoctrl = 0x2f2f2f2f,
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.mode_toyclksrc = 0x00000004, /* AUXPLL directly */
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.mode_backlight = 0x00000000,
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.mode_auxpll = 8, /* 96MHz AUXPLL */
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.lcdclk = 96, /* 96MHz AUXPLL */
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320, 320,
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240, 240,
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},
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@ -612,9 +604,8 @@ static struct panel_settings known_lcd_panels[] =
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.mode_pwmhi = 0x03400000,
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.mode_outmask = 0x00fcfcfc,
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.mode_fifoctrl = 0x2f2f2f2f,
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.mode_toyclksrc = 0x00000004, /* AUXPLL directly */
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.mode_backlight = 0x00000000,
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.mode_auxpll = 8, /* 96MHz AUXPLL */
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.lcdclk = 96,
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856, 856,
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480, 480,
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},
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@ -646,9 +637,8 @@ static struct panel_settings known_lcd_panels[] =
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.mode_pwmhi = 0x00000000,
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.mode_outmask = 0x00FFFFFF,
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.mode_fifoctrl = 0x2f2f2f2f,
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.mode_toyclksrc = 0x00000004, /* AUXPLL directly */
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.mode_backlight = 0x00000000,
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.mode_auxpll = (48/12) * 2,
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.lcdclk = 96,
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800, 800,
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480, 480,
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},
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@ -828,11 +818,17 @@ static void au1200_setpanel(struct panel_settings *newpanel,
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*/
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if (!(panel->mode_clkcontrol & LCD_CLKCONTROL_EXT))
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{
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uint32 sys_clksrc;
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alchemy_wrsys(panel->mode_auxpll, AU1000_SYS_AUXPLL);
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sys_clksrc = alchemy_rdsys(AU1000_SYS_CLKSRC) & ~0x0000001f;
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sys_clksrc |= panel->mode_toyclksrc;
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alchemy_wrsys(sys_clksrc, AU1000_SYS_CLKSRC);
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struct clk *c = clk_get(NULL, "lcd_intclk");
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long r, pc = panel->lcdclk * 1000000;
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if (!IS_ERR(c)) {
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r = clk_round_rate(c, pc);
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if ((pc - r) < (pc / 10)) { /* 10% slack */
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clk_set_rate(c, r);
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clk_prepare_enable(c);
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}
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clk_put(c);
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}
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}
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/*
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