powerpc/64s: Reimplement power4_idle code in C
This implements the tricky tracing and soft irq handling bits in C, leaving the low level bit to asm. A functional difference is that this redirects the interrupt exit to a return stub to execute blr, rather than the lr address itself. This is probably barely measurable on real hardware, but it keeps the link stack balanced. Tested with QEMU. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Move power4_fixup_nap back into exceptions-64s.S] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190711022404.18132-1-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin
Michael Ellerman
parent
30e813cf46
commit
ed0bc98f8c
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@ -412,6 +412,9 @@ static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
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extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
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extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
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extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
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#ifdef CONFIG_PPC_970_NAP
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extern void power4_idle_nap(void);
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#endif
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extern unsigned long cpuidle_disable;
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enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
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@ -62,8 +62,7 @@ obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o
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obj-$(CONFIG_PPC_BARRIER_NOSPEC) += security.o
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obj-$(CONFIG_PPC64) += vdso64/
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obj-$(CONFIG_ALTIVEC) += vecemu.o
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obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
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obj-$(CONFIG_PPC_P7_NAP) += idle_book3s.o
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obj-$(CONFIG_PPC_BOOK3S_IDLE) += idle_book3s.o
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procfs-y := proc_powerpc.o
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obj-$(CONFIG_PROC_FS) += $(procfs-y)
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rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI) := rtas_pci.o
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@ -2208,11 +2208,20 @@ __end_interrupts:
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DEFINE_FIXED_SYMBOL(__end_interrupts)
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#ifdef CONFIG_PPC_970_NAP
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/*
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* Called by exception entry code if _TLF_NAPPING was set, this clears
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* the NAPPING flag, and redirects the exception exit to
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* power4_fixup_nap_return.
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*/
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.globl power4_fixup_nap
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EXC_COMMON_BEGIN(power4_fixup_nap)
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andc r9,r9,r10
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std r9,TI_LOCAL_FLAGS(r11)
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ld r10,_LINK(r1) /* make idle task do the */
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std r10,_NIP(r1) /* equivalent of a blr */
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LOAD_REG_ADDR(r10, power4_idle_nap_return)
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std r10,_NIP(r1)
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blr
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power4_idle_nap_return:
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blr
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#endif
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@ -77,6 +77,31 @@ void arch_cpu_idle(void)
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int powersave_nap;
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#ifdef CONFIG_PPC_970_NAP
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void power4_idle(void)
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{
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if (!cpu_has_feature(CPU_FTR_CAN_NAP))
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return;
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if (!powersave_nap)
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return;
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if (!prep_irq_for_idle())
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return;
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if (cpu_has_feature(CPU_FTR_ALTIVEC))
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asm volatile("DSSALL ; sync" ::: "memory");
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power4_idle_nap();
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/*
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* power4_idle_nap returns with interrupts enabled (soft and hard).
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* to our caller with interrupts enabled (soft and hard). Our caller
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* can cope with either interrupts disabled or enabled upon return.
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*/
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}
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#endif
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#ifdef CONFIG_SYSCTL
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/*
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* Register the sysctl to set/clear powersave_nap.
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@ -15,7 +15,9 @@
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#include <asm/asm-offsets.h>
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#include <asm/ppc-opcode.h>
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#include <asm/cpuidle.h>
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#include <asm/thread_info.h> /* TLF_NAPPING */
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#ifdef CONFIG_PPC_P7_NAP
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/*
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* Desired PSSCR in r3
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*
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@ -181,4 +183,22 @@ _GLOBAL(isa206_idle_insn_mayloss)
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bne 2f
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IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
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2: IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
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#endif
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#ifdef CONFIG_PPC_970_NAP
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_GLOBAL(power4_idle_nap)
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LOAD_REG_IMMEDIATE(r7, MSR_KERNEL|MSR_EE|MSR_POW)
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ld r9,PACA_THREAD_INFO(r13)
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ld r8,TI_LOCAL_FLAGS(r9)
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ori r8,r8,_TLF_NAPPING
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std r8,TI_LOCAL_FLAGS(r9)
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/*
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* NAPPING bit is set, from this point onward power4_fixup_nap
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* will cause exceptions to return to power4_idle_nap_return.
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*/
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1: sync
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isync
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mtmsrd r7
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isync
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b 1b
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#endif
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@ -1,83 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This file contains the power_save function for 970-family CPUs.
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*/
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/irqflags.h>
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#include <asm/hw_irq.h>
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#include <asm/feature-fixups.h>
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#undef DEBUG
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.text
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_GLOBAL(power4_idle)
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BEGIN_FTR_SECTION
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blr
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END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
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/* Now check if user or arch enabled NAP mode */
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LOAD_REG_ADDRBASE(r3,powersave_nap)
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lwz r4,ADDROFF(powersave_nap)(r3)
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cmpwi 0,r4,0
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beqlr
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/* This sequence is similar to prep_irq_for_idle() */
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/* Hard disable interrupts */
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mfmsr r7
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rldicl r0,r7,48,1
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rotldi r0,r0,16
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mtmsrd r0,1
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/* Check if something happened while soft-disabled */
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lbz r0,PACAIRQHAPPENED(r13)
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cmpwi cr0,r0,0
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bne- 2f
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/*
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* Soft-enable interrupts. This will make power4_fixup_nap return
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* to our caller with interrupts enabled (soft and hard). The caller
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* can cope with either interrupts disabled or enabled upon return.
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*/
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#ifdef CONFIG_TRACE_IRQFLAGS
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/* Tell the tracer interrupts are on, because idle responds to them. */
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mflr r0
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std r0,16(r1)
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stdu r1,-128(r1)
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bl trace_hardirqs_on
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addi r1,r1,128
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ld r0,16(r1)
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mtlr r0
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mfmsr r7
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#endif /* CONFIG_TRACE_IRQFLAGS */
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li r0,IRQS_ENABLED
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stb r0,PACAIRQSOFTMASK(r13) /* we'll hard-enable shortly */
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BEGIN_FTR_SECTION
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DSSALL
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sync
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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ld r9, PACA_THREAD_INFO(r13)
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ld r8,TI_LOCAL_FLAGS(r9) /* set napping bit */
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ori r8,r8,_TLF_NAPPING /* so when we take an exception */
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std r8,TI_LOCAL_FLAGS(r9) /* it will return to our caller */
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ori r7,r7,MSR_EE
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oris r7,r7,MSR_POW@h
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1: sync
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isync
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mtmsrd r7
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isync
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b 1b
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2: /* Return if an interrupt had happened while soft disabled */
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/* Set the HARD_DIS flag because interrupts are now hard disabled */
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ori r0,r0,PACA_IRQ_HARD_DIS
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stb r0,PACAIRQHAPPENED(r13)
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blr
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@ -177,6 +177,10 @@ config PPC_970_NAP
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config PPC_P7_NAP
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bool
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config PPC_BOOK3S_IDLE
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def_bool y
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depends on (PPC_970_NAP || PPC_P7_NAP)
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config PPC_INDIRECT_PIO
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bool
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select GENERIC_IOMAP
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