Add more support for the Yukon Ultra chip found in dual core centino laptops.
The newest Yukon Ultra chipset's require more special tweaks. They seem to be like the Yukon XL chipsets. This code is transliterated from the latest SysKonnect driver; I don't have any Ultra hardware. Signed-off-by: Stephe Hemminger <shemminger@osdl.org> Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
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Stephen Hemminger
parent
72cb852920
commit
ed6d32c7a9
@ -304,7 +304,8 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
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u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
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if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
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if (sky2->autoneg == AUTONEG_ENABLE &&
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(hw->chip_id != CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
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u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
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ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
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@ -332,7 +333,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
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if (sky2->autoneg == AUTONEG_ENABLE &&
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hw->chip_id == CHIP_ID_YUKON_XL) {
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(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
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ctrl &= ~PHY_M_PC_DSC_MSK;
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ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
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}
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@ -448,10 +449,11 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
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/* set LED Function Control register */
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gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
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PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
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PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
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PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
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gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
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(PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
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PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
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PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
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PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
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/* set Polarity Control register */
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gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
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@ -465,6 +467,25 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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/* restore page register */
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gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
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break;
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case CHIP_ID_YUKON_EC_U:
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pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
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/* select page 3 to access LED control register */
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gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
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/* set LED Function Control register */
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gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
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(PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
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PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
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PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
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PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
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/* set Blink Rate in LED Timer Control Register */
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gm_phy_write(hw, port, PHY_MARV_INT_MASK,
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ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
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/* restore page register */
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gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
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break;
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default:
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/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
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@ -473,19 +494,21 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
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}
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if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
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if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
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/* apply fixes in PHY AFE */
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gm_phy_write(hw, port, 22, 255);
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pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
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gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
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/* increase differential signal amplitude in 10BASE-T */
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gm_phy_write(hw, port, 24, 0xaa99);
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gm_phy_write(hw, port, 23, 0x2011);
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gm_phy_write(hw, port, 0x18, 0xaa99);
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gm_phy_write(hw, port, 0x17, 0x2011);
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/* fix for IEEE A/B Symmetry failure in 1000BASE-T */
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gm_phy_write(hw, port, 24, 0xa204);
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gm_phy_write(hw, port, 23, 0x2002);
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gm_phy_write(hw, port, 0x18, 0xa204);
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gm_phy_write(hw, port, 0x17, 0x2002);
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/* set page register to 0 */
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gm_phy_write(hw, port, 22, 0);
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gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
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} else {
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gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
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@ -559,6 +582,11 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
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if (sky2->duplex == DUPLEX_FULL)
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reg |= GM_GPCR_DUP_FULL;
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/* turn off pause in 10/100mbps half duplex */
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else if (sky2->speed != SPEED_1000 &&
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hw->chip_id != CHIP_ID_YUKON_EC_U)
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sky2->tx_pause = sky2->rx_pause = 0;
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} else
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reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
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@ -1504,17 +1532,26 @@ static void sky2_link_up(struct sky2_port *sky2)
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sky2_write8(hw, SK_REG(port, LNK_LED_REG),
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LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
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if (hw->chip_id == CHIP_ID_YUKON_XL) {
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if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
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u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
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u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
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switch(sky2->speed) {
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case SPEED_10:
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led |= PHY_M_LEDC_INIT_CTRL(7);
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break;
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case SPEED_100:
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led |= PHY_M_LEDC_STA1_CTRL(7);
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break;
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case SPEED_1000:
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led |= PHY_M_LEDC_STA0_CTRL(7);
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break;
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}
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gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
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gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
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PHY_M_LEDC_INIT_CTRL(sky2->speed ==
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SPEED_10 ? 7 : 0) |
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PHY_M_LEDC_STA1_CTRL(sky2->speed ==
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SPEED_100 ? 7 : 0) |
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PHY_M_LEDC_STA0_CTRL(sky2->speed ==
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SPEED_1000 ? 7 : 0));
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gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
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gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
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}
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@ -1589,7 +1626,7 @@ static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
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sky2->speed = sky2_phy_speed(hw, aux);
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/* Pause bits are offset (9..8) */
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if (hw->chip_id == CHIP_ID_YUKON_XL)
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if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
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aux >>= 6;
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sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
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@ -2226,13 +2263,6 @@ static int __devinit sky2_reset(struct sky2_hw *hw)
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return -EOPNOTSUPP;
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}
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/* This chip is new and not tested yet */
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if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
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pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
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pci_name(hw->pdev));
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pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
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}
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/* disable ASF */
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if (hw->chip_id <= CHIP_ID_YUKON_EC) {
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sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
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@ -378,6 +378,9 @@ enum {
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CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
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CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
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CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
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CHIP_REV_YU_EC_U_A0 = 0,
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CHIP_REV_YU_EC_U_A1 = 1,
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};
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/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
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