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ARM: SoC fixes for 4.17

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This round of fixes has two larger changes that came in last week:
 
 - A set of a couple of patches all intended to finally turn on
   USB support on various Amlogic SoC based boards. The respective
   driver were not finalized until very late before the merge window
   and the DT portion is the last bit now.
 - A defconfig update for gemini that had repeatedly missed the
   cut but that is required to actually boot any real machines
   with the default build.
 
 The rest are the usual small changes:
 
 - A fix for a nasty build regression on the OMAP memory drivers
 - A fix for a boot problem on Intel/Altera SocFPGA
 - A MAINTAINER file update
 - A couple of fixes for issues found by automated testing
   (kernelci, coverity, sparse, ...)
 - A few incorrect DT entries are updated to match the hardware
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
 "This round of fixes has two larger changes that came in last week:

   - a couple of patches all intended to finally turn on USB support on
     various Amlogic SoC based boards. The respective driver were not
     finalized until very late before the merge window and the DT
     portion is the last bit now.

   - a defconfig update for gemini that had repeatedly missed the cut
     but that is required to actually boot any real machines with the
     default build.

  The rest are the usual small changes:

   - a fix for a nasty build regression on the OMAP memory drivers

   - a fix for a boot problem on Intel/Altera SocFPGA

   - a MAINTAINER file update

   - a couple of fixes for issues found by automated testing (kernelci,
     coverity, sparse, ...)

   - a few incorrect DT entries are updated to match the hardware"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: defconfig: Update Gemini defconfig
  ARM: s3c24xx: jive: Fix some GPIO names
  HISI LPC: Add Kconfig MFD_CORE dependency
  ARM: dts: Fix NAS4220B pin config
  MAINTAINERS: Remove myself as maintainer
  arm64: dts: correct SATA addresses for Stingray
  ARM64: dts: meson-gxm-khadas-vim2: enable the USB controller
  ARM64: dts: meson-gxl-nexbox-a95x: enable the USB controller
  ARM64: dts: meson-gxl-s905x-libretech-cc: enable the USB controller
  ARM64: dts: meson-gx-p23x-q20x: enable the USB controller
  ARM64: dts: meson-gxl-s905x-p212: enable the USB controller
  ARM64: dts: meson-gxm: add GXM specific USB host configuration
  ARM64: dts: meson-gxl: add USB host support
  ARM: OMAP2+: Fix build when using split object directories
  soc: bcm2835: Make !RASPBERRYPI_FIRMWARE dummies return failure
  soc: bcm: raspberrypi-power: Fix use of __packed
  ARM: dts: Fix cm2 and prm sizes for omap4
  ARM: socfpga_defconfig: Remove QSPI Sector 4K size force
  firmware: arm_scmi: remove redundant null check on array
  arm64: dts: juno: drop unnecessary address-cells and size-cells properties
This commit is contained in:
Linus Torvalds 2018-04-27 09:22:06 -07:00
commit ee7141c929
25 changed files with 277 additions and 148 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -1208,7 +1208,6 @@ F: drivers/*/*alpine*
ARM/ARTPEC MACHINE SUPPORT
M: Jesper Nilsson <jesper.nilsson@axis.com>
M: Lars Persson <lars.persson@axis.com>
M: Niklas Cassel <niklas.cassel@axis.com>
S: Maintained
L: linux-arm-kernel@axis.com
F: arch/arm/mach-artpec
@ -10909,7 +10908,6 @@ F: drivers/pci/host/
F: drivers/pci/dwc/
PCIE DRIVER FOR AXIS ARTPEC
M: Niklas Cassel <niklas.cassel@axis.com>
M: Jesper Nilsson <jesper.nilsson@axis.com>
L: linux-arm-kernel@axis.com
L: linux-pci@vger.kernel.org

28
arch/arm/boot/dts/gemini-nas4220b.dts
View File

@ -134,37 +134,37 @@ mux {
function = "gmii";
groups = "gmii_gmac0_grp";
};
/* Settings come from OpenWRT */
/* Settings come from OpenWRT, pins on SL3516 */
conf0 {
pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV";
pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV";
skew-delay = <0>;
};
conf1 {
pins = "T8 GMAC0 RXC", "T11 GMAC1 RXC";
pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC";
skew-delay = <15>;
};
conf2 {
pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN";
skew-delay = <7>;
};
conf3 {
pins = "V7 GMAC0 TXC";
pins = "U8 GMAC0 TXC";
skew-delay = <11>;
};
conf4 {
pins = "P10 GMAC1 TXC";
pins = "V11 GMAC1 TXC";
skew-delay = <10>;
};
conf5 {
/* The data lines all have default skew */
pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
"P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
"U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
"R7 GMAC0 TXD2", "P7 GMAC0 TXD3",
"R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
"V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
"R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
"U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
"Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
"T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
"V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
"Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
"T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
"U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
"W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
skew-delay = <7>;
};
/* Set up drive strength on GMAC0 to 16 mA */

8
arch/arm/boot/dts/omap4.dtsi
View File

@ -163,10 +163,10 @@ cm1_clockdomains: clockdomains {
cm2: cm2@8000 {
compatible = "ti,omap4-cm2", "simple-bus";
reg = <0x8000 0x3000>;
reg = <0x8000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8000 0x3000>;
ranges = <0 0x8000 0x2000>;
cm2_clocks: clocks {
#address-cells = <1>;
@ -250,11 +250,11 @@ counter32k: counter@4000 {
prm: prm@6000 {
compatible = "ti,omap4-prm";
reg = <0x6000 0x3000>;
reg = <0x6000 0x2000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x6000 0x3000>;
ranges = <0 0x6000 0x2000>;
prm_clocks: clocks {
#address-cells = <1>;

27
arch/arm/configs/gemini_defconfig
View File

@ -1,6 +1,7 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_USER_NS=y
CONFIG_RELAY=y
@ -12,15 +13,21 @@ CONFIG_ARCH_GEMINI=y
CONFIG_PCI=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_CMA=y
CONFIG_CMDLINE="console=ttyS0,115200n8"
CONFIG_KEXEC=y
CONFIG_BINFMT_MISC=y
CONFIG_PM=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
@ -33,6 +40,11 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=y
CONFIG_PATA_FTIDE010=y
CONFIG_NETDEVICES=y
CONFIG_GEMINI_ETHERNET=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_GPIO=y
CONFIG_REALTEK_PHY=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
@ -43,9 +55,19 @@ CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
CONFIG_SENSORS_GPIO_FAN=y
CONFIG_SENSORS_LM75=y
CONFIG_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_GEMINI_WATCHDOG=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_ILITEK_IL9322=y
CONFIG_DRM_TVE200=y
CONFIG_LOGO=y
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_FOTG210_HCD=y
@ -54,6 +76,7 @@ CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_DMADEVICES=y

1
arch/arm/configs/socfpga_defconfig
View File

@ -57,6 +57,7 @@ CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
CONFIG_SPI_CADENCE_QUADSPI=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_CONFIGFS=y

6
arch/arm/mach-omap2/Makefile
View File

@ -243,8 +243,4 @@ arch/arm/mach-omap2/pm-asm-offsets.s: arch/arm/mach-omap2/pm-asm-offsets.c
include/generated/ti-pm-asm-offsets.h: arch/arm/mach-omap2/pm-asm-offsets.s FORCE
$(call filechk,offsets,__TI_PM_ASM_OFFSETS_H__)
# For rule to generate ti-emif-asm-offsets.h dependency
include drivers/memory/Makefile.asm-offsets
arch/arm/mach-omap2/sleep33xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h
arch/arm/mach-omap2/sleep43xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h
$(obj)/sleep33xx.o $(obj)/sleep43xx.o: include/generated/ti-pm-asm-offsets.h

3
arch/arm/mach-omap2/pm-asm-offsets.c
View File

@ -7,9 +7,12 @@
#include <linux/kbuild.h>
#include <linux/platform_data/pm33xx.h>
#include <linux/ti-emif-sram.h>
int main(void)
{
ti_emif_asm_offsets();
DEFINE(AMX3_PM_WFI_FLAGS_OFFSET,
offsetof(struct am33xx_pm_sram_data, wfi_flags));
DEFINE(AMX3_PM_L2_AUX_CTRL_VAL_OFFSET,

1
arch/arm/mach-omap2/sleep33xx.S
View File

@ -6,7 +6,6 @@
* Dave Gerlach, Vaibhav Bedia
*/
#include <generated/ti-emif-asm-offsets.h>
#include <generated/ti-pm-asm-offsets.h>
#include <linux/linkage.h>
#include <linux/ti-emif-sram.h>

1
arch/arm/mach-omap2/sleep43xx.S
View File

@ -6,7 +6,6 @@
* Dave Gerlach, Vaibhav Bedia
*/
#include <generated/ti-emif-asm-offsets.h>
#include <generated/ti-pm-asm-offsets.h>
#include <linux/linkage.h>
#include <linux/ti-emif-sram.h>

4
arch/arm/mach-s3c24xx/mach-jive.c
View File

@ -427,9 +427,9 @@ static struct gpiod_lookup_table jive_wm8750_gpiod_table = {
.dev_id = "spi_gpio",
.table = {
GPIO_LOOKUP("GPIOB", 4,
"gpio-sck", GPIO_ACTIVE_HIGH),
"sck", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("GPIOB", 9,
"gpio-mosi", GPIO_ACTIVE_HIGH),
"mosi", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("GPIOH", 10,
"cs", GPIO_ACTIVE_HIGH),
{ },

4
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
View File

@ -212,3 +212,7 @@ &uart_AO {
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb0 {
status = "okay";
};

12
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
View File

@ -271,3 +271,15 @@ &uart_AO {
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb0 {
status = "okay";
};
&usb2_phy0 {
/*
* even though the schematics don't show it:
* HDMI_5V is also used as supply for the USB VBUS.
*/
phy-supply = <&hdmi_5v>;
};

4
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
View File

@ -215,3 +215,7 @@ &uart_AO {
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb0 {
status = "okay";
};

4
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
View File

@ -185,3 +185,7 @@ &uart_AO {
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb0 {
status = "okay";
};

61
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -20,6 +20,67 @@ secmon_reserved_alt: secmon@5000000 {
no-map;
};
};
soc {
usb0: usb@c9000000 {
status = "disabled";
compatible = "amlogic,meson-gxl-dwc3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&clkc CLKID_USB>;
clock-names = "usb_general";
resets = <&reset RESET_USB_OTG>;
reset-names = "usb_otg";
dwc3: dwc3@c9000000 {
compatible = "snps,dwc3";
reg = <0x0 0xc9000000 0x0 0x100000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
};
};
};
};
&apb {
usb2_phy0: phy@78000 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0x78000 0x0 0x20>;
clocks = <&clkc CLKID_USB>;
clock-names = "phy";
resets = <&reset RESET_USB_OTG>;
reset-names = "phy";
status = "okay";
};
usb2_phy1: phy@78020 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0x78020 0x0 0x20>;
clocks = <&clkc CLKID_USB>;
clock-names = "phy";
resets = <&reset RESET_USB_OTG>;
reset-names = "phy";
status = "okay";
};
usb3_phy: phy@78080 {
compatible = "amlogic,meson-gxl-usb3-phy";
#phy-cells = <0>;
reg = <0x0 0x78080 0x0 0x20>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
clock-names = "phy", "peripheral";
resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
reset-names = "phy", "peripheral";
status = "okay";
};
};
&ethmac {

4
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
View File

@ -406,3 +406,7 @@ &saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
};
&usb0 {
status = "okay";
};

17
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
View File

@ -80,6 +80,19 @@ cpu7: cpu@103 {
};
};
&apb {
usb2_phy2: phy@78040 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0x78040 0x0 0x20>;
clocks = <&clkc CLKID_USB>;
clock-names = "phy";
resets = <&reset RESET_USB_OTG>;
reset-names = "phy";
status = "okay";
};
};
&clkc_AO {
compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
};
@ -100,3 +113,7 @@ &vpu {
&hdmi_tx {
compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
};
&dwc3 {
phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
};

2
arch/arm64/boot/dts/arm/juno-motherboard.dtsi
View File

@ -56,8 +56,6 @@ mb_fixed_3v3: mcc-sb-3v3 {
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
power-button {
debounce_interval = <50>;

80
arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi
View File

@ -36,11 +36,11 @@ sata {
#size-cells = <1>;
ranges = <0x0 0x0 0x67d00000 0x00800000>;
sata0: ahci@210000 {
sata0: ahci@0 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00210000 0x1000>;
reg = <0x00000000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -52,9 +52,9 @@ sata0_port0: sata-port@0 {
};
};
sata_phy0: sata_phy@212100 {
sata_phy0: sata_phy@2100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00212100 0x1000>;
reg = <0x00002100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
@ -66,11 +66,11 @@ sata0_phy0: sata-phy@0 {
};
};
sata1: ahci@310000 {
sata1: ahci@10000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00310000 0x1000>;
reg = <0x00010000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -82,9 +82,9 @@ sata1_port0: sata-port@0 {
};
};
sata_phy1: sata_phy@312100 {
sata_phy1: sata_phy@12100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00312100 0x1000>;
reg = <0x00012100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
@ -96,11 +96,11 @@ sata1_phy0: sata-phy@0 {
};
};
sata2: ahci@120000 {
sata2: ahci@20000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00120000 0x1000>;
reg = <0x00020000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -112,9 +112,9 @@ sata2_port0: sata-port@0 {
};
};
sata_phy2: sata_phy@122100 {
sata_phy2: sata_phy@22100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00122100 0x1000>;
reg = <0x00022100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
@ -126,11 +126,11 @@ sata2_phy0: sata-phy@0 {
};
};
sata3: ahci@130000 {
sata3: ahci@30000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00130000 0x1000>;
reg = <0x00030000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -142,9 +142,9 @@ sata3_port0: sata-port@0 {
};
};
sata_phy3: sata_phy@132100 {
sata_phy3: sata_phy@32100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00132100 0x1000>;
reg = <0x00032100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
@ -156,11 +156,11 @@ sata3_phy0: sata-phy@0 {
};
};
sata4: ahci@330000 {
sata4: ahci@100000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00330000 0x1000>;
reg = <0x00100000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -172,9 +172,9 @@ sata4_port0: sata-port@0 {
};
};
sata_phy4: sata_phy@332100 {
sata_phy4: sata_phy@102100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00332100 0x1000>;
reg = <0x00102100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
@ -186,11 +186,11 @@ sata4_phy0: sata-phy@0 {
};
};
sata5: ahci@400000 {
sata5: ahci@110000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00400000 0x1000>;
reg = <0x00110000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -202,9 +202,9 @@ sata5_port0: sata-port@0 {
};
};
sata_phy5: sata_phy@402100 {
sata_phy5: sata_phy@112100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00402100 0x1000>;
reg = <0x00112100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
@ -216,11 +216,11 @@ sata5_phy0: sata-phy@0 {
};
};
sata6: ahci@410000 {
sata6: ahci@120000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00410000 0x1000>;
reg = <0x00120000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -232,9 +232,9 @@ sata6_port0: sata-port@0 {
};
};
sata_phy6: sata_phy@412100 {
sata_phy6: sata_phy@122100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00412100 0x1000>;
reg = <0x00122100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
@ -246,11 +246,11 @@ sata6_phy0: sata-phy@0 {
};
};
sata7: ahci@420000 {
sata7: ahci@130000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00420000 0x1000>;
reg = <0x00130000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -262,9 +262,9 @@ sata7_port0: sata-port@0 {
};
};
sata_phy7: sata_phy@422100 {
sata_phy7: sata_phy@132100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00422100 0x1000>;
reg = <0x00132100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;

1
drivers/bus/Kconfig
View File

@ -33,6 +33,7 @@ config HISILICON_LPC
bool "Support for ISA I/O space on HiSilicon Hip06/7"
depends on ARM64 && (ARCH_HISI || COMPILE_TEST)
select INDIRECT_PIO
select MFD_CORE if ACPI
help
Driver to enable I/O access to devices attached to the Low Pin
Count bus on the HiSilicon Hip06/7 SoC.

2
drivers/firmware/arm_scmi/clock.c
View File

@ -284,7 +284,7 @@ scmi_clock_info_get(const struct scmi_handle *handle, u32 clk_id)
struct clock_info *ci = handle->clk_priv;
struct scmi_clock_info *clk = ci->clk + clk_id;
if (!clk->name || !clk->name[0])
if (!clk->name[0])
return NULL;
return clk;

72
drivers/memory/emif-asm-offsets.c
View File

@ -16,77 +16,7 @@
int main(void)
{
DEFINE(EMIF_SDCFG_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_sdcfg_val));
DEFINE(EMIF_TIMING1_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_timing1_val));
DEFINE(EMIF_TIMING2_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_timing2_val));
DEFINE(EMIF_TIMING3_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_timing3_val));
DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
DEFINE(EMIF_ZQCFG_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_zqcfg_val));
DEFINE(EMIF_PMCR_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_pmcr_val));
DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
DEFINE(EMIF_COS_CONFIG_OFFSET,
offsetof(struct emif_regs_amx3, emif_cos_config));
DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_ocp_config_val));
DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));
BLANK();
DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));
DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));
DEFINE(EMIF_PM_CONFIG_OFFSET,
offsetof(struct ti_emif_pm_data, ti_emif_sram_config));
DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
offsetof(struct ti_emif_pm_data, regs_virt));
DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
offsetof(struct ti_emif_pm_data, regs_phys));
DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));
BLANK();
DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
offsetof(struct ti_emif_pm_functions, save_context));
DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
offsetof(struct ti_emif_pm_functions, restore_context));
DEFINE(EMIF_PM_ENTER_SR_OFFSET,
offsetof(struct ti_emif_pm_functions, enter_sr));
DEFINE(EMIF_PM_EXIT_SR_OFFSET,
offsetof(struct ti_emif_pm_functions, exit_sr));
DEFINE(EMIF_PM_ABORT_SR_OFFSET,
offsetof(struct ti_emif_pm_functions, abort_sr));
DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));
ti_emif_asm_offsets();
return 0;
}

2
drivers/soc/bcm/raspberrypi-power.c
View File

@ -45,7 +45,7 @@ struct rpi_power_domains {
struct rpi_power_domain_packet {
u32 domain;
u32 on;
} __packet;
};
/*
* Asks the firmware to enable or disable power on a specific power

75
include/linux/ti-emif-sram.h
View File

@ -60,6 +60,81 @@ struct ti_emif_pm_functions {
u32 abort_sr;
} __packed __aligned(8);
static inline void ti_emif_asm_offsets(void)
{
DEFINE(EMIF_SDCFG_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_sdcfg_val));
DEFINE(EMIF_TIMING1_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_timing1_val));
DEFINE(EMIF_TIMING2_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_timing2_val));
DEFINE(EMIF_TIMING3_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_timing3_val));
DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
DEFINE(EMIF_ZQCFG_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_zqcfg_val));
DEFINE(EMIF_PMCR_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_pmcr_val));
DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
DEFINE(EMIF_COS_CONFIG_OFFSET,
offsetof(struct emif_regs_amx3, emif_cos_config));
DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_ocp_config_val));
DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));
BLANK();
DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));
DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));
DEFINE(EMIF_PM_CONFIG_OFFSET,
offsetof(struct ti_emif_pm_data, ti_emif_sram_config));
DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
offsetof(struct ti_emif_pm_data, regs_virt));
DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
offsetof(struct ti_emif_pm_data, regs_phys));
DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));
BLANK();
DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
offsetof(struct ti_emif_pm_functions, save_context));
DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
offsetof(struct ti_emif_pm_functions, restore_context));
DEFINE(EMIF_PM_ENTER_SR_OFFSET,
offsetof(struct ti_emif_pm_functions, enter_sr));
DEFINE(EMIF_PM_EXIT_SR_OFFSET,
offsetof(struct ti_emif_pm_functions, exit_sr));
DEFINE(EMIF_PM_ABORT_SR_OFFSET,
offsetof(struct ti_emif_pm_functions, abort_sr));
DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));
}
struct gen_pool;
int ti_emif_copy_pm_function_table(struct gen_pool *sram_pool, void *dst);

4
include/soc/bcm2835/raspberrypi-firmware.h
View File

@ -143,13 +143,13 @@ struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node);
static inline int rpi_firmware_property(struct rpi_firmware *fw, u32 tag,
void *data, size_t len)
{
return 0;
return -ENOSYS;
}
static inline int rpi_firmware_property_list(struct rpi_firmware *fw,
void *data, size_t tag_size)
{
return 0;
return -ENOSYS;
}
static inline struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node)