Merge branch 'for-30-rc5/all-i2c' of git://git.fluff.org/bjdooks/linux
* 'for-30-rc5/all-i2c' of git://git.fluff.org/bjdooks/linux: i2c-bfin-twi: abort transfer is MEM bit is reset unexpectedly i2c-s3c2410: Remove useless break code i2c-s3c2410: Fix typo 'i2s' -> 'i2c' i2c: tegra: Assign unused slave address
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commit
f1bb20a836
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@ -193,7 +193,13 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
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return;
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}
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if (twi_int_status & MCOMP) {
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if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
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if ((read_MASTER_CTL(iface) & MEN) == 0 &&
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(iface->cur_mode == TWI_I2C_MODE_REPEAT ||
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iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
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iface->result = -1;
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write_INT_MASK(iface, 0);
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write_MASTER_CTL(iface, 0);
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} else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
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if (iface->readNum == 0) {
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/* set the read number to 1 and ask for manual
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* stop in block combine mode
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@ -248,12 +248,12 @@ static inline int is_msgend(struct s3c24xx_i2c *i2c)
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return i2c->msg_ptr >= i2c->msg->len;
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}
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/* i2s_s3c_irq_nextbyte
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/* i2c_s3c_irq_nextbyte
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*
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* process an interrupt and work out what to do
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*/
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static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
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static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
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{
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unsigned long tmp;
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unsigned char byte;
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@ -264,7 +264,6 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
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case STATE_IDLE:
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dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
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goto out;
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break;
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case STATE_STOP:
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dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
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@ -444,7 +443,7 @@ static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
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/* pretty much this leaves us with the fact that we've
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* transmitted or received whatever byte we last sent */
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i2s_s3c_irq_nextbyte(i2c, status);
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i2c_s3c_irq_nextbyte(i2c, status);
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out:
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return IRQ_HANDLED;
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@ -40,8 +40,10 @@
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#define I2C_CNFG_NEW_MASTER_FSM (1<<11)
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#define I2C_STATUS 0x01C
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#define I2C_SL_CNFG 0x020
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#define I2C_SL_CNFG_NACK (1<<1)
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#define I2C_SL_CNFG_NEWSL (1<<2)
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#define I2C_SL_ADDR1 0x02c
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#define I2C_SL_ADDR2 0x030
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#define I2C_TX_FIFO 0x050
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#define I2C_RX_FIFO 0x054
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#define I2C_PACKET_TRANSFER_STATUS 0x058
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@ -337,7 +339,11 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
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if (!i2c_dev->is_dvc) {
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u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
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i2c_writel(i2c_dev, sl_cfg | I2C_SL_CNFG_NEWSL, I2C_SL_CNFG);
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sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
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i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
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i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
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i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
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}
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val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
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