b43: Remove the PHY spinlock
This fixes a sparse warning about weird locking. The spinlock is not needed, so simply remove it. This also adds some sanity checks to the PHY and radio locking to protect against recursive locking. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -476,7 +476,6 @@ struct b43_phy {
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u16 radio_ver; /* Radio version */
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u8 radio_rev; /* Radio revision */
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bool locked; /* Only used in b43_phy_{un}lock() */
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bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
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/* ACI (adjacent channel interference) flags. */
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@ -513,11 +512,6 @@ struct b43_phy {
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s16 lna_gain; /* LNA */
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s16 pga_gain; /* PGA */
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/* PHY lock for core.rev < 3
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* This lock is only used by b43_phy_{un}lock()
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*/
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spinlock_t lock;
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/* Desired TX power level (in dBm).
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* This is set by the user and adjusted in b43_phy_xmitpower(). */
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u8 power_level;
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@ -528,9 +522,7 @@ struct b43_phy {
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struct b43_bbatt bbatt;
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struct b43_rfatt rfatt;
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u8 tx_control; /* B43_TXCTL_XXX */
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#ifdef CONFIG_B43_DEBUG
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bool manual_txpower_control; /* Manual TX-power control enabled? */
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#endif
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/* Hardware Power Control enabled? */
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bool hardware_power_control;
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@ -571,6 +563,13 @@ struct b43_phy {
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B43_OFDMTAB_DIRECTION_READ,
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B43_OFDMTAB_DIRECTION_WRITE,
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} ofdmtab_addr_direction;
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#if B43_DEBUG
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/* Manual TX-power control enabled? */
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bool manual_txpower_control;
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/* PHY registers locked by b43_phy_lock()? */
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bool phy_locked;
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#endif /* B43_DEBUG */
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};
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/* Data structures for DMA transmission, per 80211 core. */
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@ -222,8 +222,6 @@ static ssize_t txpower_g_read_file(struct b43_wldev *dev,
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static int txpower_g_write_file(struct b43_wldev *dev,
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const char *buf, size_t count)
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{
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unsigned long phy_flags;
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if (dev->phy.type != B43_PHYTYPE_G)
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return -ENODEV;
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if ((count >= 4) && (memcmp(buf, "auto", 4) == 0)) {
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@ -247,12 +245,12 @@ static int txpower_g_write_file(struct b43_wldev *dev,
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dev->phy.tx_control |= B43_TXCTL_PA2DB;
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if (pa3db)
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dev->phy.tx_control |= B43_TXCTL_PA3DB;
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b43_phy_lock(dev, phy_flags);
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b43_phy_lock(dev);
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b43_radio_lock(dev);
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b43_set_txpower_g(dev, &dev->phy.bbatt,
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&dev->phy.rfatt, dev->phy.tx_control);
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b43_radio_unlock(dev);
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b43_phy_unlock(dev, phy_flags);
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b43_phy_unlock(dev);
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}
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return 0;
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@ -3146,9 +3146,6 @@ static void setup_struct_phy_for_init(struct b43_wldev *dev,
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memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
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memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
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/* Flags */
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phy->locked = 0;
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phy->aci_enable = 0;
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phy->aci_wlan_automatic = 0;
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phy->aci_hw_rssi = 0;
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@ -3175,7 +3172,6 @@ static void setup_struct_phy_for_init(struct b43_wldev *dev,
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phy->lofcal = 0xFFFF;
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phy->initval = 0xFFFF;
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spin_lock_init(&phy->lock);
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phy->interfmode = B43_INTERFMODE_NONE;
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phy->channel = 0xFF;
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@ -228,42 +228,30 @@ static void b43_shm_clear_tssi(struct b43_wldev *dev)
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}
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}
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void b43_raw_phy_lock(struct b43_wldev *dev)
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/* Lock the PHY registers against concurrent access from the microcode.
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* This lock is nonrecursive. */
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void b43_phy_lock(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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#if B43_DEBUG
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B43_WARN_ON(dev->phy.phy_locked);
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dev->phy.phy_locked = 1;
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#endif
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B43_WARN_ON(dev->dev->id.revision < 3);
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B43_WARN_ON(!irqs_disabled());
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/* We had a check for MACCTL==0 here, but I think that doesn't
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* make sense, as MACCTL is never 0 when this is called.
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* --mb */
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B43_WARN_ON(b43_read32(dev, B43_MMIO_MACCTL) == 0);
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if (dev->dev->id.revision < 3) {
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b43_mac_suspend(dev);
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spin_lock(&phy->lock);
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} else {
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if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
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b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
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}
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phy->locked = 1;
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if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
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b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
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}
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void b43_raw_phy_unlock(struct b43_wldev *dev)
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void b43_phy_unlock(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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#if B43_DEBUG
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B43_WARN_ON(!dev->phy.phy_locked);
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dev->phy.phy_locked = 0;
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#endif
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B43_WARN_ON(dev->dev->id.revision < 3);
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B43_WARN_ON(!irqs_disabled());
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if (dev->dev->id.revision < 3) {
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if (phy->locked) {
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spin_unlock(&phy->lock);
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b43_mac_enable(dev);
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}
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} else {
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if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
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b43_power_saving_ctl_bits(dev, 0);
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}
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phy->locked = 0;
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if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
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b43_power_saving_ctl_bits(dev, 0);
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}
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/* Different PHYs require different register routing flags.
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@ -1730,7 +1718,6 @@ void b43_phy_xmitpower(struct b43_wldev *dev)
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int rfatt_delta, bbatt_delta;
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int rfatt, bbatt;
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u8 tx_control;
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unsigned long phylock_flags;
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tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
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v0 = (s8) (tmp & 0x00FF);
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@ -1861,13 +1848,13 @@ void b43_phy_xmitpower(struct b43_wldev *dev)
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phy->bbatt.att = bbatt;
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/* Adjust the hardware */
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b43_phy_lock(dev, phylock_flags);
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b43_phy_lock(dev);
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b43_radio_lock(dev);
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b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt,
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phy->tx_control);
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b43_lo_g_ctl_mark_cur_used(dev);
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b43_radio_unlock(dev);
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b43_phy_unlock(dev, phylock_flags);
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b43_phy_unlock(dev);
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break;
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}
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default:
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@ -2158,6 +2145,7 @@ void b43_radio_lock(struct b43_wldev *dev)
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u32 macctl;
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macctl = b43_read32(dev, B43_MMIO_MACCTL);
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B43_WARN_ON(macctl & B43_MACCTL_RADIOLOCK);
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macctl |= B43_MACCTL_RADIOLOCK;
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b43_write32(dev, B43_MMIO_MACCTL, macctl);
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/* Commit the write and wait for the device
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@ -2174,6 +2162,7 @@ void b43_radio_unlock(struct b43_wldev *dev)
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b43_read16(dev, B43_MMIO_PHY_VER);
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/* unlock */
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macctl = b43_read32(dev, B43_MMIO_MACCTL);
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B43_WARN_ON(!(macctl & B43_MACCTL_RADIOLOCK));
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macctl &= ~B43_MACCTL_RADIOLOCK;
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b43_write32(dev, B43_MMIO_MACCTL, macctl);
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}
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@ -2355,12 +2344,11 @@ u8 b43_radio_aci_scan(struct b43_wldev * dev)
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u8 ret[13];
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unsigned int channel = phy->channel;
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unsigned int i, j, start, end;
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unsigned long phylock_flags;
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if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
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return 0;
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b43_phy_lock(dev, phylock_flags);
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b43_phy_lock(dev);
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b43_radio_lock(dev);
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b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
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b43_phy_write(dev, B43_PHY_G_CRS,
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@ -2389,7 +2377,7 @@ u8 b43_radio_aci_scan(struct b43_wldev * dev)
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ret[j] = 1;
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}
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b43_radio_unlock(dev);
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b43_phy_unlock(dev, phylock_flags);
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b43_phy_unlock(dev);
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return ret[channel - 1];
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}
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@ -199,18 +199,8 @@ enum {
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#define B43_PHYVER_TYPE_SHIFT 8
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#define B43_PHYVER_VERSION 0x00FF
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void b43_raw_phy_lock(struct b43_wldev *dev);
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#define b43_phy_lock(dev, flags) \
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do { \
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local_irq_save(flags); \
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b43_raw_phy_lock(dev); \
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} while (0)
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void b43_raw_phy_unlock(struct b43_wldev *dev);
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#define b43_phy_unlock(dev, flags) \
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do { \
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b43_raw_phy_unlock(dev); \
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local_irq_restore(flags); \
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} while (0)
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void b43_phy_lock(struct b43_wldev *dev);
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void b43_phy_unlock(struct b43_wldev *dev);
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u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
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void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);
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