gpio: pca953x: make the register access by GPIO bank
Until now the pca953x driver accessed all the bank of a given register in a single command using only a 32 bits variable. New expanders from the pca53x family come with 40 GPIOs which no more fit in a 32 variable. This patch make access to the registers more generic by relying on an array of u8 variables. This fits exactly the way the registers are represented in the hardware. It also adds helpers to access to a single register of a bank instead of reading or writing all the banks for a given register. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Gregory CLEMENT
Linus Walleij
parent
5985d76cc1
commit
f5f0b7aa89
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@ -71,18 +71,23 @@ static const struct i2c_device_id pca953x_id[] = {
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};
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MODULE_DEVICE_TABLE(i2c, pca953x_id);
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#define MAX_BANK 5
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#define BANK_SZ 8
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#define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
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struct pca953x_chip {
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unsigned gpio_start;
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u32 reg_output;
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u32 reg_direction;
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u8 reg_output[MAX_BANK];
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u8 reg_direction[MAX_BANK];
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struct mutex i2c_lock;
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#ifdef CONFIG_GPIO_PCA953X_IRQ
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struct mutex irq_lock;
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u32 irq_mask;
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u32 irq_stat;
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u32 irq_trig_raise;
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u32 irq_trig_fall;
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u8 irq_mask[MAX_BANK];
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u8 irq_stat[MAX_BANK];
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u8 irq_trig_raise[MAX_BANK];
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u8 irq_trig_fall[MAX_BANK];
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int irq_base;
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struct irq_domain *domain;
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#endif
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@ -93,33 +98,69 @@ struct pca953x_chip {
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int chip_type;
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};
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static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val)
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static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
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int off)
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{
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int ret;
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int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
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int offset = off / BANK_SZ;
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ret = i2c_smbus_read_byte_data(chip->client,
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(reg << bank_shift) + offset);
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*val = ret;
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if (ret < 0) {
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dev_err(&chip->client->dev, "failed reading register\n");
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return ret;
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}
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return 0;
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}
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static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
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int off)
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{
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int ret = 0;
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int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
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int offset = off / BANK_SZ;
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ret = i2c_smbus_write_byte_data(chip->client,
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(reg << bank_shift) + offset, val);
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if (ret < 0) {
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dev_err(&chip->client->dev, "failed writing register\n");
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return ret;
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}
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return 0;
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}
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static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
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{
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int ret = 0;
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if (chip->gpio_chip.ngpio <= 8)
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ret = i2c_smbus_write_byte_data(chip->client, reg, val);
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else if (chip->gpio_chip.ngpio == 24) {
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cpu_to_le32s(&val);
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ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
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else if (chip->gpio_chip.ngpio >= 24) {
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int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
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ret = i2c_smbus_write_i2c_block_data(chip->client,
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(reg << 2) | REG_ADDR_AI,
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3,
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(u8 *) &val);
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(reg << bank_shift) | REG_ADDR_AI,
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NBANK(chip), val);
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}
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else {
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switch (chip->chip_type) {
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case PCA953X_TYPE:
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ret = i2c_smbus_write_word_data(chip->client,
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reg << 1, val);
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reg << 1, (u16) *val);
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break;
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case PCA957X_TYPE:
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ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
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val & 0xff);
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val[0]);
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if (ret < 0)
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break;
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ret = i2c_smbus_write_byte_data(chip->client,
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(reg << 1) + 1,
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(val & 0xff00) >> 8);
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val[1]);
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break;
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}
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}
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@ -132,26 +173,24 @@ static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val)
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return 0;
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}
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static int pca953x_read_reg(struct pca953x_chip *chip, int reg, u32 *val)
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static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
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{
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int ret;
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if (chip->gpio_chip.ngpio <= 8) {
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ret = i2c_smbus_read_byte_data(chip->client, reg);
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*val = ret;
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}
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else if (chip->gpio_chip.ngpio == 24) {
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*val = 0;
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} else if (chip->gpio_chip.ngpio >= 24) {
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int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
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ret = i2c_smbus_read_i2c_block_data(chip->client,
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(reg << 2) | REG_ADDR_AI,
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3,
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(u8 *) val);
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le32_to_cpus(val);
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(reg << bank_shift) | REG_ADDR_AI,
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NBANK(chip), val);
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} else {
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ret = i2c_smbus_read_word_data(chip->client, reg << 1);
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*val = ret;
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val[0] = (u16)ret & 0xFF;
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val[1] = (u16)ret >> 8;
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}
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if (ret < 0) {
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dev_err(&chip->client->dev, "failed reading register\n");
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return ret;
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@ -163,13 +202,13 @@ static int pca953x_read_reg(struct pca953x_chip *chip, int reg, u32 *val)
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static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
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{
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struct pca953x_chip *chip;
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uint reg_val;
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u8 reg_val;
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int ret, offset = 0;
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chip = container_of(gc, struct pca953x_chip, gpio_chip);
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mutex_lock(&chip->i2c_lock);
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reg_val = chip->reg_direction | (1u << off);
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reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
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switch (chip->chip_type) {
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case PCA953X_TYPE:
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@ -179,11 +218,11 @@ static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
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offset = PCA957X_CFG;
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break;
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}
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ret = pca953x_write_reg(chip, offset, reg_val);
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ret = pca953x_write_single(chip, offset, reg_val, off);
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if (ret)
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goto exit;
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chip->reg_direction = reg_val;
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chip->reg_direction[off / BANK_SZ] = reg_val;
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ret = 0;
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exit:
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mutex_unlock(&chip->i2c_lock);
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@ -194,7 +233,7 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
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unsigned off, int val)
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{
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struct pca953x_chip *chip;
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uint reg_val;
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u8 reg_val;
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int ret, offset = 0;
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chip = container_of(gc, struct pca953x_chip, gpio_chip);
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@ -202,9 +241,11 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
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mutex_lock(&chip->i2c_lock);
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/* set output level */
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if (val)
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reg_val = chip->reg_output | (1u << off);
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reg_val = chip->reg_output[off / BANK_SZ]
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| (1u << (off % BANK_SZ));
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else
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reg_val = chip->reg_output & ~(1u << off);
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reg_val = chip->reg_output[off / BANK_SZ]
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& ~(1u << (off % BANK_SZ));
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switch (chip->chip_type) {
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case PCA953X_TYPE:
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@ -214,14 +255,14 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
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offset = PCA957X_OUT;
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break;
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}
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ret = pca953x_write_reg(chip, offset, reg_val);
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ret = pca953x_write_single(chip, offset, reg_val, off);
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if (ret)
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goto exit;
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chip->reg_output = reg_val;
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chip->reg_output[off / BANK_SZ] = reg_val;
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/* then direction */
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reg_val = chip->reg_direction & ~(1u << off);
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reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
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switch (chip->chip_type) {
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case PCA953X_TYPE:
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offset = PCA953X_DIRECTION;
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@ -230,11 +271,11 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
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offset = PCA957X_CFG;
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break;
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}
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ret = pca953x_write_reg(chip, offset, reg_val);
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ret = pca953x_write_single(chip, offset, reg_val, off);
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if (ret)
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goto exit;
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chip->reg_direction = reg_val;
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chip->reg_direction[off / BANK_SZ] = reg_val;
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ret = 0;
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exit:
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mutex_unlock(&chip->i2c_lock);
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@ -258,7 +299,7 @@ static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
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offset = PCA957X_IN;
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break;
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}
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ret = pca953x_read_reg(chip, offset, ®_val);
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ret = pca953x_read_single(chip, offset, ®_val, off);
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mutex_unlock(&chip->i2c_lock);
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if (ret < 0) {
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/* NOTE: diagnostic already emitted; that's all we should
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@ -274,16 +315,18 @@ static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
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static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
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{
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struct pca953x_chip *chip;
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u32 reg_val;
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u8 reg_val;
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int ret, offset = 0;
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chip = container_of(gc, struct pca953x_chip, gpio_chip);
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mutex_lock(&chip->i2c_lock);
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if (val)
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reg_val = chip->reg_output | (1u << off);
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reg_val = chip->reg_output[off / BANK_SZ]
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| (1u << (off % BANK_SZ));
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else
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reg_val = chip->reg_output & ~(1u << off);
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reg_val = chip->reg_output[off / BANK_SZ]
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& ~(1u << (off % BANK_SZ));
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switch (chip->chip_type) {
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case PCA953X_TYPE:
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@ -293,11 +336,11 @@ static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
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offset = PCA957X_OUT;
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break;
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}
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ret = pca953x_write_reg(chip, offset, reg_val);
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ret = pca953x_write_single(chip, offset, reg_val, off);
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if (ret)
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goto exit;
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chip->reg_output = reg_val;
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chip->reg_output[off / BANK_SZ] = reg_val;
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exit:
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mutex_unlock(&chip->i2c_lock);
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}
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@ -335,14 +378,14 @@ static void pca953x_irq_mask(struct irq_data *d)
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{
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struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
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chip->irq_mask &= ~(1 << d->hwirq);
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chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
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}
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static void pca953x_irq_unmask(struct irq_data *d)
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{
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struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
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chip->irq_mask |= 1 << d->hwirq;
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chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
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}
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static void pca953x_irq_bus_lock(struct irq_data *d)
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@ -355,17 +398,20 @@ static void pca953x_irq_bus_lock(struct irq_data *d)
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static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
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{
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struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
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u32 new_irqs;
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u32 level;
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u8 new_irqs;
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int level, i;
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/* Look for any newly setup interrupt */
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new_irqs = chip->irq_trig_fall | chip->irq_trig_raise;
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new_irqs &= ~chip->reg_direction;
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for (i = 0; i < NBANK(chip); i++) {
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new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
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new_irqs &= ~chip->reg_direction[i];
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while (new_irqs) {
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level = __ffs(new_irqs);
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pca953x_gpio_direction_input(&chip->gpio_chip, level);
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new_irqs &= ~(1 << level);
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while (new_irqs) {
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level = __ffs(new_irqs);
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pca953x_gpio_direction_input(&chip->gpio_chip,
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level + (BANK_SZ * i));
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new_irqs &= ~(1 << level);
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}
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}
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mutex_unlock(&chip->irq_lock);
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@ -374,7 +420,8 @@ static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
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static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << d->hwirq;
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int bank_nb = d->hwirq / BANK_SZ;
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u8 mask = 1 << (d->hwirq % BANK_SZ);
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if (!(type & IRQ_TYPE_EDGE_BOTH)) {
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dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
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@ -383,14 +430,14 @@ static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
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}
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if (type & IRQ_TYPE_EDGE_FALLING)
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chip->irq_trig_fall |= mask;
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chip->irq_trig_fall[bank_nb] |= mask;
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else
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chip->irq_trig_fall &= ~mask;
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chip->irq_trig_fall[bank_nb] &= ~mask;
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if (type & IRQ_TYPE_EDGE_RISING)
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chip->irq_trig_raise |= mask;
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chip->irq_trig_raise[bank_nb] |= mask;
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else
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chip->irq_trig_raise &= ~mask;
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chip->irq_trig_raise[bank_nb] &= ~mask;
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return 0;
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}
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@ -404,13 +451,13 @@ static struct irq_chip pca953x_irq_chip = {
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.irq_set_type = pca953x_irq_set_type,
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};
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static u32 pca953x_irq_pending(struct pca953x_chip *chip)
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static u8 pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
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{
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u32 cur_stat;
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u32 old_stat;
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u32 pending;
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u32 trigger;
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int ret, offset = 0;
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u8 cur_stat[MAX_BANK];
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u8 old_stat[MAX_BANK];
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u8 pendings = 0;
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u8 trigger[MAX_BANK], triggers = 0;
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int ret, i, offset = 0;
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switch (chip->chip_type) {
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case PCA953X_TYPE:
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@ -420,45 +467,54 @@ static u32 pca953x_irq_pending(struct pca953x_chip *chip)
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offset = PCA957X_IN;
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break;
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}
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ret = pca953x_read_reg(chip, offset, &cur_stat);
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ret = pca953x_read_regs(chip, offset, cur_stat);
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if (ret)
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return 0;
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/* Remove output pins from the equation */
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cur_stat &= chip->reg_direction;
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for (i = 0; i < NBANK(chip); i++)
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cur_stat[i] &= chip->reg_direction[i];
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old_stat = chip->irq_stat;
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trigger = (cur_stat ^ old_stat) & chip->irq_mask;
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memcpy(old_stat, chip->irq_stat, NBANK(chip));
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if (!trigger)
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for (i = 0; i < NBANK(chip); i++) {
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trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
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triggers += trigger[i];
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}
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if (!triggers)
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return 0;
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chip->irq_stat = cur_stat;
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memcpy(chip->irq_stat, cur_stat, NBANK(chip));
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pending = (old_stat & chip->irq_trig_fall) |
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(cur_stat & chip->irq_trig_raise);
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pending &= trigger;
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for (i = 0; i < NBANK(chip); i++) {
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pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
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(cur_stat[i] & chip->irq_trig_raise[i]);
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pending[i] &= trigger[i];
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pendings += pending[i];
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}
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return pending;
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return pendings;
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}
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|
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static irqreturn_t pca953x_irq_handler(int irq, void *devid)
|
||||
{
|
||||
struct pca953x_chip *chip = devid;
|
||||
u32 pending;
|
||||
u32 level;
|
||||
u8 pending[MAX_BANK];
|
||||
u8 level;
|
||||
int i;
|
||||
|
||||
pending = pca953x_irq_pending(chip);
|
||||
|
||||
if (!pending)
|
||||
if (!pca953x_irq_pending(chip, pending))
|
||||
return IRQ_HANDLED;
|
||||
|
||||
do {
|
||||
level = __ffs(pending);
|
||||
handle_nested_irq(irq_find_mapping(chip->domain, level));
|
||||
|
||||
pending &= ~(1 << level);
|
||||
} while (pending);
|
||||
for (i = 0; i < NBANK(chip); i++) {
|
||||
while (pending[i]) {
|
||||
level = __ffs(pending[i]);
|
||||
handle_nested_irq(irq_find_mapping(chip->domain,
|
||||
level + (BANK_SZ * i)));
|
||||
pending[i] &= ~(1 << level);
|
||||
}
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
@ -468,8 +524,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
|
|||
int irq_base)
|
||||
{
|
||||
struct i2c_client *client = chip->client;
|
||||
int ret, offset = 0;
|
||||
u32 temporary;
|
||||
int ret, i, offset = 0;
|
||||
|
||||
if (irq_base != -1
|
||||
&& (id->driver_data & PCA_INT)) {
|
||||
|
|
@ -483,8 +538,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
|
|||
offset = PCA957X_IN;
|
||||
break;
|
||||
}
|
||||
ret = pca953x_read_reg(chip, offset, &temporary);
|
||||
chip->irq_stat = temporary;
|
||||
ret = pca953x_read_regs(chip, offset, chip->irq_stat);
|
||||
if (ret)
|
||||
goto out_failed;
|
||||
|
||||
|
|
@ -493,7 +547,8 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
|
|||
* interrupt. We have to rely on the previous read for
|
||||
* this purpose.
|
||||
*/
|
||||
chip->irq_stat &= chip->reg_direction;
|
||||
for (i = 0; i < NBANK(chip); i++)
|
||||
chip->irq_stat[i] &= chip->reg_direction[i];
|
||||
mutex_init(&chip->irq_lock);
|
||||
|
||||
chip->irq_base = irq_alloc_descs(-1, irq_base, chip->gpio_chip.ngpio, -1);
|
||||
|
|
@ -619,18 +674,24 @@ pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
|
|||
static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
|
||||
{
|
||||
int ret;
|
||||
u8 val[MAX_BANK];
|
||||
|
||||
ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output);
|
||||
ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = pca953x_read_reg(chip, PCA953X_DIRECTION,
|
||||
&chip->reg_direction);
|
||||
ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
|
||||
chip->reg_direction);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* set platform specific polarity inversion */
|
||||
ret = pca953x_write_reg(chip, PCA953X_INVERT, invert);
|
||||
if (invert)
|
||||
memset(val, 0xFF, NBANK(chip));
|
||||
else
|
||||
memset(val, 0, NBANK(chip));
|
||||
|
||||
ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -638,28 +699,36 @@ static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
|
|||
static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
|
||||
{
|
||||
int ret;
|
||||
u32 val = 0;
|
||||
u8 val[MAX_BANK];
|
||||
|
||||
/* Let every port in proper state, that could save power */
|
||||
pca953x_write_reg(chip, PCA957X_PUPD, 0x0);
|
||||
pca953x_write_reg(chip, PCA957X_CFG, 0xffff);
|
||||
pca953x_write_reg(chip, PCA957X_OUT, 0x0);
|
||||
memset(val, 0, NBANK(chip));
|
||||
pca953x_write_regs(chip, PCA957X_PUPD, val);
|
||||
memset(val, 0xFF, NBANK(chip));
|
||||
pca953x_write_regs(chip, PCA957X_CFG, val);
|
||||
memset(val, 0, NBANK(chip));
|
||||
pca953x_write_regs(chip, PCA957X_OUT, val);
|
||||
|
||||
ret = pca953x_read_reg(chip, PCA957X_IN, &val);
|
||||
ret = pca953x_read_regs(chip, PCA957X_IN, val);
|
||||
if (ret)
|
||||
goto out;
|
||||
ret = pca953x_read_reg(chip, PCA957X_OUT, &chip->reg_output);
|
||||
ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
|
||||
if (ret)
|
||||
goto out;
|
||||
ret = pca953x_read_reg(chip, PCA957X_CFG, &chip->reg_direction);
|
||||
ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* set platform specific polarity inversion */
|
||||
pca953x_write_reg(chip, PCA957X_INVRT, invert);
|
||||
if (invert)
|
||||
memset(val, 0xFF, NBANK(chip));
|
||||
else
|
||||
memset(val, 0, NBANK(chip));
|
||||
pca953x_write_regs(chip, PCA957X_INVRT, val);
|
||||
|
||||
/* To enable register 6, 7 to controll pull up and pull down */
|
||||
pca953x_write_reg(chip, PCA957X_BKEN, 0x202);
|
||||
memset(val, 0x02, NBANK(chip));
|
||||
pca953x_write_regs(chip, PCA957X_BKEN, val);
|
||||
|
||||
return 0;
|
||||
out:
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user