RDMA/cxgb4: Update some HW limits
Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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@ -41,11 +41,13 @@
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#define T4_MAX_NUM_QP (1<<16)
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#define T4_MAX_NUM_CQ (1<<15)
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#define T4_MAX_NUM_PD (1<<15)
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#define T4_MAX_PBL_SIZE 256
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#define T4_MAX_RQ_SIZE 1024
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#define T4_MAX_SQ_SIZE 1024
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#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE-1)
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#define T4_MAX_CQ_DEPTH 8192
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#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
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#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
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#define T4_MAX_IQ_SIZE (65520 - 1)
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#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
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#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
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#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
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#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
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#define T4_MAX_NUM_STAG (1<<15)
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#define T4_MAX_MR_SIZE (~0ULL - 1)
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#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
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@ -79,12 +81,11 @@ struct t4_status_page {
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sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
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#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
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sizeof(struct fw_ri_immd)))
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#define T4_MAX_FR_DEPTH 255
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#define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
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#define T4_RQ_NUM_SLOTS 2
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#define T4_RQ_NUM_BYTES (T4_EQ_SIZE * T4_RQ_NUM_SLOTS)
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#define T4_MAX_RECV_SGE ((T4_RQ_NUM_BYTES - sizeof(struct fw_ri_recv_wr) - \
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sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
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#define T4_MAX_RECV_SGE 4
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union t4_wr {
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struct fw_ri_res_wr res;
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