pinctrl: ocelot: Add Sparx5 SoC support
This add support for Sparx5 pinctrl, using the ocelot drives as basis. It adds pinconfig support as well, as supported by the platform. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200615133242.24911-6-lars.povlsen@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Lars Povlsen
Linus Walleij
parent
f088ab6d4f
commit
f8a7476077
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@ -25,6 +25,23 @@
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#include "pinconf.h"
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#include "pinmux.h"
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#define ocelot_clrsetbits(addr, clear, set) \
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writel((readl(addr) & ~(clear)) | (set), (addr))
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/* PINCONFIG bits (sparx5 only) */
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enum {
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PINCONF_BIAS,
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PINCONF_SCHMITT,
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PINCONF_DRIVE_STRENGTH,
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};
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#define BIAS_PD_BIT BIT(4)
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#define BIAS_PU_BIT BIT(3)
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#define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT)
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#define SCHMITT_BIT BIT(2)
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#define DRIVE_BITS GENMASK(1, 0)
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/* GPIO standard registers */
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#define OCELOT_GPIO_OUT_SET 0x0
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#define OCELOT_GPIO_OUT_CLR 0x4
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#define OCELOT_GPIO_OUT 0x8
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@ -42,12 +59,17 @@
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enum {
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FUNC_NONE,
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FUNC_GPIO,
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FUNC_IRQ0,
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FUNC_IRQ0_IN,
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FUNC_IRQ0_OUT,
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FUNC_IRQ1,
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FUNC_IRQ1_IN,
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FUNC_IRQ1_OUT,
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FUNC_EXT_IRQ,
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FUNC_MIIM,
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FUNC_PHY_LED,
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FUNC_PCI_WAKE,
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FUNC_MD,
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FUNC_PTP0,
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FUNC_PTP1,
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FUNC_PTP2,
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@ -59,24 +81,36 @@ enum {
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FUNC_SG1,
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FUNC_SG2,
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FUNC_SI,
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FUNC_SI2,
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FUNC_TACHO,
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FUNC_TWI,
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FUNC_TWI2,
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FUNC_TWI3,
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FUNC_TWI_SCL_M,
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FUNC_UART,
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FUNC_UART2,
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FUNC_UART3,
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FUNC_PLL_STAT,
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FUNC_EMMC,
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FUNC_REF_CLK,
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FUNC_RCVRD_CLK,
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FUNC_MAX
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};
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static const char *const ocelot_function_names[] = {
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[FUNC_NONE] = "none",
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[FUNC_GPIO] = "gpio",
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[FUNC_IRQ0] = "irq0",
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[FUNC_IRQ0_IN] = "irq0_in",
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[FUNC_IRQ0_OUT] = "irq0_out",
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[FUNC_IRQ1] = "irq1",
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[FUNC_IRQ1_IN] = "irq1_in",
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[FUNC_IRQ1_OUT] = "irq1_out",
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[FUNC_EXT_IRQ] = "ext_irq",
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[FUNC_MIIM] = "miim",
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[FUNC_PHY_LED] = "phy_led",
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[FUNC_PCI_WAKE] = "pci_wake",
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[FUNC_MD] = "md",
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[FUNC_PTP0] = "ptp0",
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[FUNC_PTP1] = "ptp1",
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[FUNC_PTP2] = "ptp2",
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@ -88,12 +122,19 @@ static const char *const ocelot_function_names[] = {
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[FUNC_SG1] = "sg1",
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[FUNC_SG2] = "sg2",
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[FUNC_SI] = "si",
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[FUNC_SI2] = "si2",
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[FUNC_TACHO] = "tacho",
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[FUNC_TWI] = "twi",
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[FUNC_TWI2] = "twi2",
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[FUNC_TWI3] = "twi3",
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[FUNC_TWI_SCL_M] = "twi_scl_m",
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[FUNC_UART] = "uart",
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[FUNC_UART2] = "uart2",
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[FUNC_UART3] = "uart3",
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[FUNC_PLL_STAT] = "pll_stat",
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[FUNC_EMMC] = "emmc",
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[FUNC_REF_CLK] = "ref_clk",
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[FUNC_RCVRD_CLK] = "rcvrd_clk",
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};
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struct ocelot_pmx_func {
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@ -111,6 +152,7 @@ struct ocelot_pinctrl {
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struct pinctrl_dev *pctl;
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struct gpio_chip gpio_chip;
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struct regmap *map;
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void __iomem *pincfg;
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struct pinctrl_desc *desc;
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struct ocelot_pmx_func func[FUNC_MAX];
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u8 stride;
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@ -324,6 +366,152 @@ static const struct pinctrl_pin_desc jaguar2_pins[] = {
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JAGUAR2_PIN(63),
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};
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#define SPARX5_P(p, f0, f1, f2) \
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static struct ocelot_pin_caps sparx5_pin_##p = { \
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.pin = p, \
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.functions = { \
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FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
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}, \
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}
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SPARX5_P(0, SG0, PLL_STAT, NONE);
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SPARX5_P(1, SG0, NONE, NONE);
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SPARX5_P(2, SG0, NONE, NONE);
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SPARX5_P(3, SG0, NONE, NONE);
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SPARX5_P(4, SG1, NONE, NONE);
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SPARX5_P(5, SG1, NONE, NONE);
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SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
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SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
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SPARX5_P(8, PTP0, NONE, SFP);
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SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
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SPARX5_P(10, UART, NONE, NONE);
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SPARX5_P(11, UART, NONE, NONE);
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SPARX5_P(12, SG1, NONE, NONE);
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SPARX5_P(13, SG1, NONE, NONE);
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SPARX5_P(14, TWI, TWI_SCL_M, NONE);
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SPARX5_P(15, TWI, NONE, NONE);
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SPARX5_P(16, SI, TWI_SCL_M, SFP);
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SPARX5_P(17, SI, TWI_SCL_M, SFP);
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SPARX5_P(18, SI, TWI_SCL_M, SFP);
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SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
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SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
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SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
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SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
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SPARX5_P(23, PWM, UART3, TWI_SCL_M);
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SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
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SPARX5_P(25, PTP3, SI, TWI_SCL_M);
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SPARX5_P(26, UART2, SI, TWI_SCL_M);
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SPARX5_P(27, UART2, SI, TWI_SCL_M);
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SPARX5_P(28, TWI2, SI, SFP);
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SPARX5_P(29, TWI2, SI, SFP);
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SPARX5_P(30, SG2, SI, PWM);
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SPARX5_P(31, SG2, SI, TWI_SCL_M);
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SPARX5_P(32, SG2, SI, TWI_SCL_M);
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SPARX5_P(33, SG2, SI, SFP);
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SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
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SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
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SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
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SPARX5_P(37, SFP, NONE, EMMC);
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SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
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SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
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SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
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SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
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SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
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SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
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SPARX5_P(44, SI, SFP, EMMC);
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SPARX5_P(45, SI, SFP, EMMC);
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SPARX5_P(46, NONE, SFP, EMMC);
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SPARX5_P(47, NONE, SFP, EMMC);
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SPARX5_P(48, TWI3, SI, SFP);
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SPARX5_P(49, TWI3, NONE, SFP);
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SPARX5_P(50, SFP, NONE, TWI_SCL_M);
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SPARX5_P(51, SFP, SI, TWI_SCL_M);
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SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
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SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
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SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
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SPARX5_P(55, SFP, PTP3, PCI_WAKE);
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SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
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SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
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SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
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SPARX5_P(59, MIIM, SFP, NONE);
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SPARX5_P(60, RECO_CLK, NONE, NONE);
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SPARX5_P(61, RECO_CLK, NONE, NONE);
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SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
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SPARX5_P(63, RECO_CLK, NONE, NONE);
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#define SPARX5_PIN(n) { \
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.number = n, \
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.name = "GPIO_"#n, \
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.drv_data = &sparx5_pin_##n \
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}
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static const struct pinctrl_pin_desc sparx5_pins[] = {
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SPARX5_PIN(0),
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SPARX5_PIN(1),
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SPARX5_PIN(2),
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SPARX5_PIN(3),
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SPARX5_PIN(4),
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SPARX5_PIN(5),
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SPARX5_PIN(6),
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SPARX5_PIN(7),
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SPARX5_PIN(8),
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SPARX5_PIN(9),
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SPARX5_PIN(10),
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SPARX5_PIN(11),
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SPARX5_PIN(12),
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SPARX5_PIN(13),
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SPARX5_PIN(14),
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SPARX5_PIN(15),
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SPARX5_PIN(16),
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SPARX5_PIN(17),
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SPARX5_PIN(18),
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SPARX5_PIN(19),
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SPARX5_PIN(20),
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SPARX5_PIN(21),
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SPARX5_PIN(22),
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SPARX5_PIN(23),
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SPARX5_PIN(24),
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SPARX5_PIN(25),
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SPARX5_PIN(26),
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SPARX5_PIN(27),
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SPARX5_PIN(28),
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SPARX5_PIN(29),
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SPARX5_PIN(30),
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SPARX5_PIN(31),
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SPARX5_PIN(32),
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SPARX5_PIN(33),
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SPARX5_PIN(34),
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SPARX5_PIN(35),
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SPARX5_PIN(36),
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SPARX5_PIN(37),
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SPARX5_PIN(38),
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SPARX5_PIN(39),
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SPARX5_PIN(40),
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SPARX5_PIN(41),
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SPARX5_PIN(42),
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SPARX5_PIN(43),
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SPARX5_PIN(44),
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SPARX5_PIN(45),
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SPARX5_PIN(46),
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SPARX5_PIN(47),
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SPARX5_PIN(48),
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SPARX5_PIN(49),
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SPARX5_PIN(50),
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SPARX5_PIN(51),
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SPARX5_PIN(52),
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SPARX5_PIN(53),
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SPARX5_PIN(54),
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SPARX5_PIN(55),
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SPARX5_PIN(56),
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SPARX5_PIN(57),
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SPARX5_PIN(58),
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SPARX5_PIN(59),
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SPARX5_PIN(60),
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SPARX5_PIN(61),
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SPARX5_PIN(62),
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SPARX5_PIN(63),
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};
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static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(ocelot_function_names);
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@ -382,6 +570,7 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
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* ALT[1]
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* This is racy because both registers can't be updated at the same time
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* but it doesn't matter much for now.
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* Note: ALT0/ALT1 are organized specially for 64 gpio targets
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*/
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regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
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BIT(p), f << p);
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@ -458,6 +647,219 @@ static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
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return 0;
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}
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static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
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unsigned int pin,
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unsigned int reg,
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int *val)
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{
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int ret = -EOPNOTSUPP;
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if (info->pincfg) {
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u32 regcfg = readl(info->pincfg + (pin * sizeof(u32)));
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ret = 0;
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switch (reg) {
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case PINCONF_BIAS:
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*val = regcfg & BIAS_BITS;
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break;
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case PINCONF_SCHMITT:
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*val = regcfg & SCHMITT_BIT;
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break;
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case PINCONF_DRIVE_STRENGTH:
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*val = regcfg & DRIVE_BITS;
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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}
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}
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return ret;
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}
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static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
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unsigned int pin,
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unsigned int reg,
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int val)
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{
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int ret = -EOPNOTSUPP;
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if (info->pincfg) {
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void __iomem *regaddr = info->pincfg + (pin * sizeof(u32));
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ret = 0;
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switch (reg) {
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case PINCONF_BIAS:
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ocelot_clrsetbits(regaddr, BIAS_BITS, val);
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break;
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case PINCONF_SCHMITT:
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ocelot_clrsetbits(regaddr, SCHMITT_BIT, val);
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break;
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case PINCONF_DRIVE_STRENGTH:
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if (val <= 3)
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ocelot_clrsetbits(regaddr, DRIVE_BITS, val);
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else
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ret = -EINVAL;
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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}
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}
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return ret;
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}
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static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned int pin, unsigned long *config)
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{
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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u32 param = pinconf_to_config_param(*config);
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int val, err;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
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if (err)
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return err;
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if (param == PIN_CONFIG_BIAS_DISABLE)
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val = (val == 0 ? true : false);
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else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
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val = (val & BIAS_PD_BIT ? true : false);
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else /* PIN_CONFIG_BIAS_PULL_UP */
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val = (val & BIAS_PU_BIT ? true : false);
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
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if (err)
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return err;
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val = (val & SCHMITT_BIT ? true : false);
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
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&val);
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if (err)
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return err;
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break;
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case PIN_CONFIG_OUTPUT:
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err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
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&val);
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if (err)
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return err;
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val = !!(val & BIT(pin % 32));
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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case PIN_CONFIG_OUTPUT_ENABLE:
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err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
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&val);
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if (err)
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return err;
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val = val & BIT(pin % 32);
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if (param == PIN_CONFIG_OUTPUT_ENABLE)
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val = !!val;
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else
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val = !val;
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break;
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default:
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return -EOPNOTSUPP;
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}
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*config = pinconf_to_config_packed(param, val);
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return 0;
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}
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static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *configs, unsigned int num_configs)
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{
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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u32 param, arg, p;
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int cfg, err = 0;
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for (cfg = 0; cfg < num_configs; cfg++) {
|
||||
param = pinconf_to_config_param(configs[cfg]);
|
||||
arg = pinconf_to_config_argument(configs[cfg]);
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
|
||||
(param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
|
||||
BIAS_PD_BIT;
|
||||
|
||||
err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
|
||||
if (err)
|
||||
goto err;
|
||||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
|
||||
arg = arg ? SCHMITT_BIT : 0;
|
||||
err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
|
||||
arg);
|
||||
if (err)
|
||||
goto err;
|
||||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
err = ocelot_hw_set_value(info, pin,
|
||||
PINCONF_DRIVE_STRENGTH,
|
||||
arg);
|
||||
if (err)
|
||||
goto err;
|
||||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_OUTPUT_ENABLE:
|
||||
case PIN_CONFIG_INPUT_ENABLE:
|
||||
case PIN_CONFIG_OUTPUT:
|
||||
p = pin % 32;
|
||||
if (arg)
|
||||
regmap_write(info->map,
|
||||
REG(OCELOT_GPIO_OUT_SET, info,
|
||||
pin),
|
||||
BIT(p));
|
||||
else
|
||||
regmap_write(info->map,
|
||||
REG(OCELOT_GPIO_OUT_CLR, info,
|
||||
pin),
|
||||
BIT(p));
|
||||
regmap_update_bits(info->map,
|
||||
REG(OCELOT_GPIO_OE, info, pin),
|
||||
BIT(p),
|
||||
param == PIN_CONFIG_INPUT_ENABLE ?
|
||||
0 : BIT(p));
|
||||
break;
|
||||
|
||||
default:
|
||||
err = -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
err:
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct pinconf_ops ocelot_confops = {
|
||||
.is_generic = true,
|
||||
.pin_config_get = ocelot_pinconf_get,
|
||||
.pin_config_set = ocelot_pinconf_set,
|
||||
.pin_config_config_dbg_show = pinconf_generic_dump_config,
|
||||
};
|
||||
|
||||
static const struct pinctrl_ops ocelot_pctl_ops = {
|
||||
.get_groups_count = ocelot_pctl_get_groups_count,
|
||||
.get_group_name = ocelot_pctl_get_group_name,
|
||||
|
|
@ -484,6 +886,16 @@ static struct pinctrl_desc jaguar2_desc = {
|
|||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc sparx5_desc = {
|
||||
.name = "sparx5-pinctrl",
|
||||
.pins = sparx5_pins,
|
||||
.npins = ARRAY_SIZE(sparx5_pins),
|
||||
.pctlops = &ocelot_pctl_ops,
|
||||
.pmxops = &ocelot_pmx_ops,
|
||||
.confops = &ocelot_confops,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int ocelot_create_group_func_map(struct device *dev,
|
||||
struct ocelot_pinctrl *info)
|
||||
{
|
||||
|
|
@ -511,7 +923,8 @@ static int ocelot_create_group_func_map(struct device *dev,
|
|||
}
|
||||
|
||||
for (i = 0; i < npins; i++)
|
||||
info->func[f].groups[i] = info->desc->pins[pins[i]].name;
|
||||
info->func[f].groups[i] =
|
||||
info->desc->pins[pins[i]].name;
|
||||
}
|
||||
|
||||
kfree(pins);
|
||||
|
|
@ -744,6 +1157,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
|
|||
static const struct of_device_id ocelot_pinctrl_of_match[] = {
|
||||
{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
|
||||
{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
|
||||
{ .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
@ -752,6 +1166,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
|
|||
struct device *dev = &pdev->dev;
|
||||
struct ocelot_pinctrl *info;
|
||||
void __iomem *base;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
struct regmap_config regmap_config = {
|
||||
.reg_bits = 32,
|
||||
|
|
@ -773,6 +1188,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
info->stride = 1 + (info->desc->npins - 1) / 32;
|
||||
|
||||
regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
|
||||
|
||||
info->map = devm_regmap_init_mmio(dev, base, ®map_config);
|
||||
|
|
@ -783,6 +1199,16 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
|
|||
dev_set_drvdata(dev, info->map);
|
||||
info->dev = dev;
|
||||
|
||||
/* Pinconf registers */
|
||||
if (info->desc->confops) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n");
|
||||
else
|
||||
info->pincfg = base;
|
||||
}
|
||||
|
||||
ret = ocelot_pinctrl_register(pdev, info);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -791,6 +1217,8 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
dev_info(dev, "driver registered\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user