sh: Kill off the remaining ST40 cruft.
The ST40 stuff in-tree hasn't built for some time, and hasn't been updated for over 3 years. ST maintains their own out-of-tree changes and rebases occasionally, and that's ultimately where all of the ST40 users go anyways. In order for the ST40 code to be brought up to date most of the stuff removed in this changeset would have to be rewritten anyways, so there's very little benefit in keeping the remnants around either. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
07782cec9b
commit
f966918724
@ -5,7 +5,6 @@
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obj-y += pci.o
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obj-$(CONFIG_PCI_AUTO) += pci-auto.o
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obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
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@ -1,488 +0,0 @@
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/*
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* Support functions for the ST40 PCI hardware.
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*/
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#include <linux/kernel.h>
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#include <linux/smp.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <asm/pci.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h> /* irqreturn_t */
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#include "pci-st40.h"
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/* This is in P2 of course */
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#define ST40PCI_BASE_ADDRESS (0xb0000000)
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#define ST40PCI_MEM_ADDRESS (ST40PCI_BASE_ADDRESS+0x0)
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#define ST40PCI_IO_ADDRESS (ST40PCI_BASE_ADDRESS+0x06000000)
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#define ST40PCI_REG_ADDRESS (ST40PCI_BASE_ADDRESS+0x07000000)
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#define ST40PCI_REG(x) (ST40PCI_REG_ADDRESS+(ST40PCI_##x))
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#define ST40PCI_REG_INDEXED(reg, index) \
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(ST40PCI_REG(reg##0) + \
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((ST40PCI_REG(reg##1) - ST40PCI_REG(reg##0))*index))
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#define ST40PCI_WRITE(reg,val) writel((val),ST40PCI_REG(reg))
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#define ST40PCI_WRITE_SHORT(reg,val) writew((val),ST40PCI_REG(reg))
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#define ST40PCI_WRITE_BYTE(reg,val) writeb((val),ST40PCI_REG(reg))
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#define ST40PCI_WRITE_INDEXED(reg, index, val) \
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writel((val), ST40PCI_REG_INDEXED(reg, index));
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#define ST40PCI_READ(reg) readl(ST40PCI_REG(reg))
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#define ST40PCI_READ_SHORT(reg) readw(ST40PCI_REG(reg))
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#define ST40PCI_READ_BYTE(reg) readb(ST40PCI_REG(reg))
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#define ST40PCI_SERR_IRQ 64
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#define ST40PCI_ERR_IRQ 65
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/* Macros to extract PLL params */
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#define PLL_MDIV(reg) ( ((unsigned)reg) & 0xff )
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#define PLL_NDIV(reg) ( (((unsigned)reg)>>8) & 0xff )
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#define PLL_PDIV(reg) ( (((unsigned)reg)>>16) & 0x3 )
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#define PLL_SETUP(reg) ( (((unsigned)reg)>>19) & 0x1ff )
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/* Build up the appropriate settings */
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#define PLL_SET(mdiv,ndiv,pdiv,setup) \
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( ((mdiv)&0xff) | (((ndiv)&0xff)<<8) | (((pdiv)&3)<<16)| (((setup)&0x1ff)<<19))
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#define PLLPCICR (0xbb040000+0x10)
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#define PLLPCICR_POWERON (1<<28)
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#define PLLPCICR_OUT_EN (1<<29)
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#define PLLPCICR_LOCKSELECT (1<<30)
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#define PLLPCICR_LOCK (1<<31)
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#define PLL_25MHZ 0x793c8512
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#define PLL_33MHZ PLL_SET(18,88,3,295)
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static void pci_set_rbar_region(unsigned int region, unsigned long localAddr,
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unsigned long pciOffset, unsigned long regionSize);
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static __init void SetPCIPLL(void)
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{
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{
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/* Lets play with the PLL values */
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unsigned long pll1cr1;
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unsigned long mdiv, ndiv, pdiv;
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unsigned long muxcr;
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unsigned int muxcr_ratios[4] = { 8, 16, 21, 1 };
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unsigned int freq;
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#define CLKGENA 0xbb040000
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#define CLKGENA_PLL2_MUXCR CLKGENA + 0x48
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pll1cr1 = ctrl_inl(PLLPCICR);
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printk("PLL1CR1 %08lx\n", pll1cr1);
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mdiv = PLL_MDIV(pll1cr1);
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ndiv = PLL_NDIV(pll1cr1);
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pdiv = PLL_PDIV(pll1cr1);
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printk("mdiv %02lx ndiv %02lx pdiv %02lx\n", mdiv, ndiv, pdiv);
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freq = ((2*27*ndiv)/mdiv) / (1 << pdiv);
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printk("PLL freq %dMHz\n", freq);
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muxcr = ctrl_inl(CLKGENA_PLL2_MUXCR);
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printk("PCI freq %dMhz\n", freq / muxcr_ratios[muxcr & 3]);
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}
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}
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struct pci_err {
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unsigned mask;
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const char *error_string;
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};
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static struct pci_err int_error[]={
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{ INT_MNLTDIM,"MNLTDIM: Master non-lock transfer"},
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{ INT_TTADI, "TTADI: Illegal byte enable in I/O transfer"},
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{ INT_TMTO, "TMTO: Target memory read/write timeout"},
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{ INT_MDEI, "MDEI: Master function disable error"},
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{ INT_APEDI, "APEDI: Address parity error"},
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{ INT_SDI, "SDI: SERR detected"},
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{ INT_DPEITW, "DPEITW: Data parity error target write"},
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{ INT_PEDITR, "PEDITR: PERR detected"},
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{ INT_TADIM, "TADIM: Target abort detected"},
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{ INT_MADIM, "MADIM: Master abort detected"},
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{ INT_MWPDI, "MWPDI: PERR from target at data write"},
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{ INT_MRDPEI, "MRDPEI: Master read data parity error"}
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};
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#define NUM_PCI_INT_ERRS ARRAY_SIZE(int_error)
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static struct pci_err aint_error[]={
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{ AINT_MBI, "MBI: Master broken"},
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{ AINT_TBTOI, "TBTOI: Target bus timeout"},
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{ AINT_MBTOI, "MBTOI: Master bus timeout"},
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{ AINT_TAI, "TAI: Target abort"},
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{ AINT_MAI, "MAI: Master abort"},
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{ AINT_RDPEI, "RDPEI: Read data parity"},
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{ AINT_WDPE, "WDPE: Write data parity"}
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};
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#define NUM_PCI_AINT_ERRS ARRAY_SIZE(aint_error)
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static void print_pci_errors(unsigned reg,struct pci_err *error,int num_errors)
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{
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int i;
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for(i=0;i<num_errors;i++) {
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if(reg & error[i].mask) {
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printk("%s\n",error[i].error_string);
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}
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}
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}
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static char * pci_commands[16]={
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"Int Ack",
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"Special Cycle",
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"I/O Read",
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"I/O Write",
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"Reserved",
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"Reserved",
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"Memory Read",
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"Memory Write",
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"Reserved",
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"Reserved",
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"Configuration Read",
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"Configuration Write",
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"Memory Read Multiple",
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"Dual Address Cycle",
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"Memory Read Line",
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"Memory Write-and-Invalidate"
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};
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static irqreturn_t st40_pci_irq(int irq, void *dev_instance)
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{
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unsigned pci_int, pci_air, pci_cir, pci_aint;
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static int count=0;
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pci_int = ST40PCI_READ(INT);pci_aint = ST40PCI_READ(AINT);
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pci_cir = ST40PCI_READ(CIR);pci_air = ST40PCI_READ(AIR);
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/* Reset state to stop multiple interrupts */
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ST40PCI_WRITE(INT, ~0); ST40PCI_WRITE(AINT, ~0);
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if(++count>1) return IRQ_HANDLED;
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printk("** PCI ERROR **\n");
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if(pci_int) {
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printk("** INT register status\n");
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print_pci_errors(pci_int,int_error,NUM_PCI_INT_ERRS);
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}
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if(pci_aint) {
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printk("** AINT register status\n");
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print_pci_errors(pci_aint,aint_error,NUM_PCI_AINT_ERRS);
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}
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printk("** Address and command info\n");
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printk("** Command %s : Address 0x%x\n",
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pci_commands[pci_cir&0xf],pci_air);
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if(pci_cir&CIR_PIOTEM) {
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printk("CIR_PIOTEM:PIO transfer error for master\n");
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}
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if(pci_cir&CIR_RWTET) {
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printk("CIR_RWTET:Read/Write transfer error for target\n");
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}
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return IRQ_HANDLED;
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}
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/* Rounds a number UP to the nearest power of two. Used for
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* sizing the PCI window.
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*/
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static u32 r2p2(u32 num)
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{
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int i = 31;
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u32 tmp = num;
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if (num == 0)
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return 0;
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do {
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if (tmp & (1 << 31))
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break;
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i--;
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tmp <<= 1;
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} while (i >= 0);
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tmp = 1 << i;
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/* If the original number isn't a power of 2, round it up */
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if (tmp != num)
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tmp <<= 1;
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return tmp;
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}
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static void __init pci_fixup_ide_bases(struct pci_dev *d)
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{
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int i;
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/*
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* PCI IDE controllers use non-standard I/O port decoding, respect it.
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*/
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if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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printk("PCI: IDE base address fixup for %s\n", pci_name(d));
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for(i=0; i<4; i++) {
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struct resource *r = &d->resource[i];
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if ((r->start & ~0x80) == 0x374) {
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r->start |= 2;
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r->end = r->start;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
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int __init st40pci_init(unsigned memStart, unsigned memSize)
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{
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u32 lsr0;
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SetPCIPLL();
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/* Initialises the ST40 pci subsystem, performing a reset, then programming
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* up the address space decoders appropriately
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*/
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/* Should reset core here as well methink */
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ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_SOFT_RESET);
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/* Loop while core resets */
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while (ST40PCI_READ(CR) & CR_SOFT_RESET);
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/* Switch off interrupts */
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ST40PCI_WRITE(INTM, 0);
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ST40PCI_WRITE(AINT, 0);
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/* Now, lets reset all the cards on the bus with extreme prejudice */
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ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_RSTCTL);
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udelay(250);
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/* Set bus active, take it out of reset */
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ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_BMAM | CR_CFINT | CR_PFCS | CR_PFE);
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/* The PCI spec says that no access must be made to the bus until 1 second
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* after reset. This seem ludicrously long, but some delay is needed here
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*/
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mdelay(1000);
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/* Switch off interrupts */
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ST40PCI_WRITE(INTM, 0);
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ST40PCI_WRITE(AINT, 0);
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/* Allow it to be a master */
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ST40PCI_WRITE_SHORT(CSR_CMD,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_IO);
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/* Access to the 0xb0000000 -> 0xb6000000 area will go through to 0x10000000 -> 0x16000000
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* on the PCI bus. This allows a nice 1-1 bus to phys mapping.
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*/
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ST40PCI_WRITE(MBR, 0x10000000);
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/* Always set the max size 128M (actually, it is only 96MB wide) */
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ST40PCI_WRITE(MBMR, 0x07ff0000);
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/* I/O addresses are mapped at 0xb6000000 -> 0xb7000000. These are changed to 0, to
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* allow cards that have legacy io such as vga to function correctly. This gives a
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* maximum of 64K of io/space as only the bottom 16 bits of the address are copied
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* over to the bus when the transaction is made. 64K of io space is more than enough
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*/
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ST40PCI_WRITE(IOBR, 0x0);
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/* Set up the 64K window */
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ST40PCI_WRITE(IOBMR, 0x0);
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/* Now we set up the mbars so the PCI bus can see the local memory */
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/* Expose a 256M window starting at PCI address 0... */
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ST40PCI_WRITE(CSR_MBAR0, 0);
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ST40PCI_WRITE(LSR0, 0x0fff0001);
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/* ... and set up the initial incoming window to expose all of RAM */
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pci_set_rbar_region(7, memStart, memStart, memSize);
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/* Maximise timeout values */
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ST40PCI_WRITE_BYTE(CSR_TRDY, 0xff);
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ST40PCI_WRITE_BYTE(CSR_RETRY, 0xff);
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ST40PCI_WRITE_BYTE(CSR_MIT, 0xff);
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ST40PCI_WRITE_BYTE(PERF,PERF_MASTER_WRITE_POSTING);
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return 1;
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}
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char * __devinit pcibios_setup(char *str)
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{
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return str;
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}
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#define SET_CONFIG_BITS(bus,devfn,where)\
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(((bus) << 16) | ((devfn) << 8) | ((where) & ~3) | (bus!=0))
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#define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where)
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static int CheckForMasterAbort(void)
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{
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if (ST40PCI_READ(INT) & INT_MADIM) {
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/* Should we clear config space version as well ??? */
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ST40PCI_WRITE(INT, INT_MADIM);
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ST40PCI_WRITE_SHORT(CSR_STATUS, 0);
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return 1;
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}
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return 0;
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}
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/* Write to config register */
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static int st40pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
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{
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ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
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switch (size) {
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case 1:
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*val = (u8)ST40PCI_READ_BYTE(PDR + (where & 3));
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break;
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case 2:
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*val = (u16)ST40PCI_READ_SHORT(PDR + (where & 2));
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break;
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case 4:
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*val = ST40PCI_READ(PDR);
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break;
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}
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if (CheckForMasterAbort()){
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switch (size) {
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case 1:
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*val = (u8)0xff;
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break;
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case 2:
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*val = (u16)0xffff;
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break;
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case 4:
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*val = 0xffffffff;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int st40pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
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{
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ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
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switch (size) {
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case 1:
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ST40PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
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break;
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case 2:
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ST40PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
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break;
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case 4:
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ST40PCI_WRITE(PDR, val);
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break;
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}
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CheckForMasterAbort();
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops st40pci_config_ops = {
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.read = st40pci_read,
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.write = st40pci_write,
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};
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/* Everything hangs off this */
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static struct pci_bus *pci_root_bus;
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static int __init pcibios_init(void)
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{
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extern unsigned long memory_start, memory_end;
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printk(KERN_ALERT "pci-st40.c: pcibios_init\n");
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if (sh_mv.mv_init_pci != NULL) {
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sh_mv.mv_init_pci();
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}
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/* The pci subsytem needs to know where memory is and how much
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* of it there is. I've simply made these globals. A better mechanism
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* is probably needed.
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*/
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st40pci_init(PHYSADDR(memory_start),
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PHYSADDR(memory_end) - PHYSADDR(memory_start));
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if (request_irq(ST40PCI_ERR_IRQ, st40_pci_irq,
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IRQF_DISABLED, "st40pci", NULL)) {
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printk(KERN_ERR "st40pci: Cannot hook interrupt\n");
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return -EIO;
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}
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/* Enable the PCI interrupts on the device */
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ST40PCI_WRITE(INTM, ~0);
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ST40PCI_WRITE(AINT, ~0);
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/* Map the io address apprioately */
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#ifdef CONFIG_HD64465
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hd64465_port_map(PCIBIOS_MIN_IO, (64 * 1024) - PCIBIOS_MIN_IO + 1,
|
||||
ST40_IO_ADDR + PCIBIOS_MIN_IO, 0);
|
||||
#endif
|
||||
|
||||
/* ok, do the scan man */
|
||||
pci_root_bus = pci_scan_bus(0, &st40pci_config_ops, NULL);
|
||||
pci_assign_unassigned_resources();
|
||||
|
||||
return 0;
|
||||
}
|
||||
subsys_initcall(pcibios_init);
|
||||
|
||||
/*
|
||||
* Publish a region of local address space over the PCI bus
|
||||
* to other devices.
|
||||
*/
|
||||
static void pci_set_rbar_region(unsigned int region, unsigned long localAddr,
|
||||
unsigned long pciOffset, unsigned long regionSize)
|
||||
{
|
||||
unsigned long mask;
|
||||
|
||||
if (region > 7)
|
||||
return;
|
||||
|
||||
if (regionSize > (512 * 1024 * 1024))
|
||||
return;
|
||||
|
||||
mask = r2p2(regionSize) - 0x10000;
|
||||
|
||||
/* Disable the region (in case currently in use, should never happen) */
|
||||
ST40PCI_WRITE_INDEXED(RSR, region, 0);
|
||||
|
||||
/* Start of local address space to publish */
|
||||
ST40PCI_WRITE_INDEXED(RLAR, region, PHYSADDR(localAddr) );
|
||||
|
||||
/* Start of region in PCI address space as an offset from MBAR0 */
|
||||
ST40PCI_WRITE_INDEXED(RBAR, region, pciOffset);
|
||||
|
||||
/* Size of region */
|
||||
ST40PCI_WRITE_INDEXED(RSR, region, mask | 1);
|
||||
}
|
||||
|
||||
@ -1,136 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
|
||||
*
|
||||
* May be copied or modified under the terms of the GNU General Public
|
||||
* License. See linux/COPYING for more information.
|
||||
*
|
||||
* Definitions for the ST40 PCI hardware.
|
||||
*/
|
||||
|
||||
#ifndef __PCI_ST40_H__
|
||||
#define __PCI_ST40_H__
|
||||
|
||||
#define ST40PCI_VCR_STATUS 0x00
|
||||
|
||||
#define ST40PCI_VCR_VERSION 0x08
|
||||
|
||||
#define ST40PCI_CR 0x10
|
||||
|
||||
#define CR_SOFT_RESET (1<<12)
|
||||
#define CR_PFCS (1<<11)
|
||||
#define CR_PFE (1<<9)
|
||||
#define CR_BMAM (1<<6)
|
||||
#define CR_HOST (1<<5)
|
||||
#define CR_CLKEN (1<<4)
|
||||
#define CR_SOCS (1<<3)
|
||||
#define CR_IOCS (1<<2)
|
||||
#define CR_RSTCTL (1<<1)
|
||||
#define CR_CFINT (1<<0)
|
||||
#define CR_LOCK_MASK 0x5a000000
|
||||
|
||||
|
||||
#define ST40PCI_LSR0 0X14
|
||||
#define ST40PCI_LAR0 0x1c
|
||||
|
||||
#define ST40PCI_INT 0x24
|
||||
#define INT_MNLTDIM (1<<15)
|
||||
#define INT_TTADI (1<<14)
|
||||
#define INT_TMTO (1<<9)
|
||||
#define INT_MDEI (1<<8)
|
||||
#define INT_APEDI (1<<7)
|
||||
#define INT_SDI (1<<6)
|
||||
#define INT_DPEITW (1<<5)
|
||||
#define INT_PEDITR (1<<4)
|
||||
#define INT_TADIM (1<<3)
|
||||
#define INT_MADIM (1<<2)
|
||||
#define INT_MWPDI (1<<1)
|
||||
#define INT_MRDPEI (1<<0)
|
||||
|
||||
|
||||
#define ST40PCI_INTM 0x28
|
||||
#define ST40PCI_AIR 0x2c
|
||||
|
||||
#define ST40PCI_CIR 0x30
|
||||
#define CIR_PIOTEM (1<<31)
|
||||
#define CIR_RWTET (1<<26)
|
||||
|
||||
#define ST40PCI_AINT 0x40
|
||||
#define AINT_MBI (1<<13)
|
||||
#define AINT_TBTOI (1<<12)
|
||||
#define AINT_MBTOI (1<<11)
|
||||
#define AINT_TAI (1<<3)
|
||||
#define AINT_MAI (1<<2)
|
||||
#define AINT_RDPEI (1<<1)
|
||||
#define AINT_WDPE (1<<0)
|
||||
|
||||
#define ST40PCI_AINTM 0x44
|
||||
#define ST40PCI_BMIR 0x48
|
||||
#define ST40PCI_PAR 0x4c
|
||||
#define ST40PCI_MBR 0x50
|
||||
#define ST40PCI_IOBR 0x54
|
||||
#define ST40PCI_PINT 0x58
|
||||
#define ST40PCI_PINTM 0x5c
|
||||
#define ST40PCI_MBMR 0x70
|
||||
#define ST40PCI_IOBMR 0x74
|
||||
#define ST40PCI_PDR 0x78
|
||||
|
||||
/* H8 specific registers start here */
|
||||
#define ST40PCI_WCBAR 0x7c
|
||||
#define ST40PCI_LOCCFG_UNLOCK 0x34
|
||||
|
||||
#define ST40PCI_RBAR0 0x100
|
||||
#define ST40PCI_RSR0 0x104
|
||||
#define ST40PCI_RLAR0 0x108
|
||||
|
||||
#define ST40PCI_RBAR1 0x110
|
||||
#define ST40PCI_RSR1 0x114
|
||||
#define ST40PCI_RLAR1 0x118
|
||||
|
||||
|
||||
#define ST40PCI_RBAR2 0x120
|
||||
#define ST40PCI_RSR2 0x124
|
||||
#define ST40PCI_RLAR2 0x128
|
||||
|
||||
#define ST40PCI_RBAR3 0x130
|
||||
#define ST40PCI_RSR3 0x134
|
||||
#define ST40PCI_RLAR3 0x138
|
||||
|
||||
#define ST40PCI_RBAR4 0x140
|
||||
#define ST40PCI_RSR4 0x144
|
||||
#define ST40PCI_RLAR4 0x148
|
||||
|
||||
#define ST40PCI_RBAR5 0x150
|
||||
#define ST40PCI_RSR5 0x154
|
||||
#define ST40PCI_RLAR5 0x158
|
||||
|
||||
#define ST40PCI_RBAR6 0x160
|
||||
#define ST40PCI_RSR6 0x164
|
||||
#define ST40PCI_RLAR6 0x168
|
||||
|
||||
#define ST40PCI_RBAR7 0x170
|
||||
#define ST40PCI_RSR7 0x174
|
||||
#define ST40PCI_RLAR7 0x178
|
||||
|
||||
|
||||
#define ST40PCI_RBAR(n) (0x100+(0x10*(n)))
|
||||
#define ST40PCI_RSR(n) (0x104+(0x10*(n)))
|
||||
#define ST40PCI_RLAR(n) (0x108+(0x10*(n)))
|
||||
|
||||
#define ST40PCI_PERF 0x80
|
||||
#define PERF_MASTER_WRITE_POSTING (1<<4)
|
||||
/* H8 specific registers end here */
|
||||
|
||||
|
||||
/* These are configs space registers */
|
||||
#define ST40PCI_CSR_VID 0x10000
|
||||
#define ST40PCI_CSR_DID 0x10002
|
||||
#define ST40PCI_CSR_CMD 0x10004
|
||||
#define ST40PCI_CSR_STATUS 0x10006
|
||||
#define ST40PCI_CSR_MBAR0 0x10010
|
||||
#define ST40PCI_CSR_TRDY 0x10040
|
||||
#define ST40PCI_CSR_RETRY 0x10041
|
||||
#define ST40PCI_CSR_MIT 0x1000d
|
||||
|
||||
#define ST40_IO_ADDR 0xb6000000
|
||||
|
||||
#endif /* __PCI_ST40_H__ */
|
||||
@ -139,14 +139,6 @@ int __init detect_cpu_and_cache_system(void)
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
|
||||
CPU_HAS_LLSC;
|
||||
break;
|
||||
case 0x8000:
|
||||
boot_cpu_data.type = CPU_ST40RA;
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU;
|
||||
break;
|
||||
case 0x8100:
|
||||
boot_cpu_data.type = CPU_ST40GX1;
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU;
|
||||
break;
|
||||
case 0x700:
|
||||
boot_cpu_data.type = CPU_SH4_501;
|
||||
boot_cpu_data.icache.ways = 2;
|
||||
|
||||
@ -303,7 +303,6 @@ static const char *cpu_name[] = {
|
||||
[CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
|
||||
[CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
|
||||
[CPU_SH7760] = "SH7760",
|
||||
[CPU_ST40RA] = "ST40RA", [CPU_ST40GX1] = "ST40GX1",
|
||||
[CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
|
||||
[CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
|
||||
[CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
|
||||
|
||||
@ -17,7 +17,7 @@ config CPU_SH4
|
||||
bool
|
||||
select CPU_HAS_INTEVT
|
||||
select CPU_HAS_SR_RB
|
||||
select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
|
||||
select CPU_HAS_PTEA if !CPU_SH4A || CPU_SHX2
|
||||
select CPU_HAS_FPU if !CPU_SH4AL_DSP
|
||||
|
||||
config CPU_SH4A
|
||||
@ -29,10 +29,6 @@ config CPU_SH4AL_DSP
|
||||
select CPU_SH4A
|
||||
select CPU_HAS_DSP
|
||||
|
||||
config CPU_SUBTYPE_ST40
|
||||
bool
|
||||
select CPU_SH4
|
||||
|
||||
config CPU_SHX2
|
||||
bool
|
||||
|
||||
@ -152,21 +148,6 @@ config CPU_SUBTYPE_SH4_202
|
||||
bool "Support SH4-202 processor"
|
||||
select CPU_SH4
|
||||
|
||||
# ST40 Processor Support
|
||||
|
||||
config CPU_SUBTYPE_ST40STB1
|
||||
bool "Support ST40STB1/ST40RA processors"
|
||||
select CPU_SUBTYPE_ST40
|
||||
help
|
||||
Select ST40STB1 if you have a ST40RA CPU.
|
||||
This was previously called the ST40STB1, hence the option name.
|
||||
|
||||
config CPU_SUBTYPE_ST40GX1
|
||||
bool "Support ST40GX1 processor"
|
||||
select CPU_SUBTYPE_ST40
|
||||
help
|
||||
Select ST40GX1 if you have a ST40GX1 CPU.
|
||||
|
||||
# SH-4A Processor Support
|
||||
|
||||
config CPU_SUBTYPE_SH7770
|
||||
|
||||
@ -102,12 +102,6 @@
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
|
||||
# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
|
||||
# include <asm/hardware.h>
|
||||
# define SCIF_BASE_ADDR 0x01030000
|
||||
@ -116,8 +110,7 @@
|
||||
# define SCIF_LSR2_OFFS 0x0000024
|
||||
# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
|
||||
# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
|
||||
TE=1,RE=1,REIE=1 */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
@ -577,15 +570,6 @@ static inline int sci_rxd_in(struct uart_port *port)
|
||||
return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffe00000)
|
||||
return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
|
||||
else
|
||||
return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
|
||||
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
|
||||
@ -49,7 +49,7 @@ enum cpu_type {
|
||||
|
||||
/* SH-4 types */
|
||||
CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
|
||||
CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
|
||||
CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
|
||||
|
||||
/* SH-4A types */
|
||||
CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user