ASoC: tlv320dac33: Internal clocking changes
During validation of the internal clocking setup it has been found that the following settings were not configured in an optimal way: ASRC_CTRL_A: SRCLKDIV was incorrect, instad of divide ratio 3, ratio of 2 has to be used (as the comment stated) DAC_CTRL_A: Fs = Fsref is the desired configuration instead of Fs = Fsref / 1.5 Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -778,7 +778,7 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
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if (dac33->fifo_mode) {
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/* Generic for all FIFO modes */
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/* 50-51 : ASRC Control registers */
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dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */
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dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
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dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
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/* Write registers 0x34 and 0x35 (MSB, LSB) */
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@ -1062,7 +1062,7 @@ static void dac33_init_chip(struct snd_soc_codec *codec)
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{
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/* 44-46: DAC Control Registers */
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/* A : DAC sample rate Fsref/1.5 */
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dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(1));
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dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
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/* B : DAC src=normal, not muted */
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dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
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DAC33_DACSRCL_LEFT);
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