Commit Graph

10 Commits

Author SHA1 Message Date
Kevin D. Kissell
8531a35e5e [MIPS] SMTC: Fix SMTC dyntick support.
Rework of SMTC support to make it work with the new clock event system,
allowing "tickless" operation, and to make it compatible with the use of
the "wait_irqoff" idle loop.  The new clocking scheme means that the
previously optional IPI instant replay mechanism is now required, and has
been made more robust.

Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-03 17:58:58 +01:00
Ralf Baechle
5aa85c9fc4 [MIPS] Handle R4000/R4400 mfc0 from count register.
The R4000 and R4400 have an errata where if the cp0 count register is read
in the exact moment when it matches the compare register no interrupt will
be generated.

This bug may be triggered if the cp0 count register is being used as
clocksource and the compare interrupt as clockevent.  So a simple
workaround is to avoid using the compare for both facilities on the
affected CPUs.

This is different from the workaround suggested in the old errata documents;
at some opportunity probably the official version should be implemented
and tested.  Another thing to find out is which processor versions
exactly are affected.  I only have errata documents upto R4400 V3.0
available so for the moment the code treats all R4000 and R4400 as broken.

This is potencially a problem for some machines that have no other decent
clocksource available; this workaround will cause them to fall back to
another clocksource, worst case the "jiffies" source.
2007-11-26 17:26:14 +00:00
Ralf Baechle
aea6863944 [MIPS] time: Fix negated condition in cevt-r4k driver.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:13 +00:00
Ralf Baechle
38760d40ca [MIPS] time: Replace plat_timer_setup with modern APIs.
plat_timer_setup is no longer getting called.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:36 +00:00
Atsushi Nemoto
3a6c43a787 [MIPS] time: Make c0_compare_int_usable faster
Try increasingly longer time periods starting of at 0x10 cycles.  This
should be fast on hardware and work nicely with emulators.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Atsushi Nemoto
c637fecb4f [MIPS] time: Fix cevt-r4k.c for 64-bit kernel
The expression "(long)(read_c0_count() - cnt)" can never be a negative
value on 64-bit kernel.  Cast to "int" before comparison.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Yoichi Yuasa
22df3f53e3 [MIPS] Add mips_hpt_frequency check to mips_clockevent_init().
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Atsushi Nemoto
dab969c00b [MIPS] time: Make c0_compare_int_usable more bullet proof
Use write_c0_compare(read_c0_count()) to clear interrupt.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-22 22:09:01 +01:00
Ralf Baechle
f887b93e17 [MIPS] SMTC: Build fix.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-19 18:15:57 +01:00
Ralf Baechle
42f77542f4 [MIPS] time: Move R4000 clockevent device code to separate configurable file
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-18 18:11:47 +01:00