a05ce88ab3
Replace several device node absolute path lookups in the mv64x60 bootwrapper code with lookups by compatible or device_type properties. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Acked-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
572 lines
14 KiB
C
572 lines
14 KiB
C
/*
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* Motorola ECC prpmc280/f101 & prpmc2800/f101e platform code.
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2007 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <stdarg.h>
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#include <stddef.h>
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#include "types.h"
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#include "elf.h"
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#include "page.h"
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#include "string.h"
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#include "stdio.h"
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#include "io.h"
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#include "ops.h"
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#include "gunzip_util.h"
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#include "mv64x60.h"
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#define KB 1024U
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#define MB (KB*KB)
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#define GB (KB*MB)
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#define MHz (1000U*1000U)
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#define GHz (1000U*MHz)
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#define BOARD_MODEL "PrPMC2800"
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#define BOARD_MODEL_MAX 32 /* max strlen(BOARD_MODEL) + 1 */
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#define EEPROM2_ADDR 0xa4
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#define EEPROM3_ADDR 0xa8
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BSS_STACK(16*KB);
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static u8 *bridge_base;
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typedef enum {
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BOARD_MODEL_PRPMC280,
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BOARD_MODEL_PRPMC2800,
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} prpmc2800_board_model;
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typedef enum {
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BRIDGE_TYPE_MV64360,
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BRIDGE_TYPE_MV64362,
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} prpmc2800_bridge_type;
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struct prpmc2800_board_info {
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prpmc2800_board_model model;
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char variant;
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prpmc2800_bridge_type bridge_type;
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u8 subsys0;
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u8 subsys1;
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u8 vpd4;
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u8 vpd4_mask;
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u32 core_speed;
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u32 mem_size;
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u32 boot_flash;
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u32 user_flash;
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};
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static struct prpmc2800_board_info prpmc2800_board_info[] = {
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{
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.model = BOARD_MODEL_PRPMC280,
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.variant = 'a',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xff,
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.subsys1 = 0xff,
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.vpd4 = 0x00,
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.vpd4_mask = 0x0f,
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.core_speed = 1*GHz,
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.mem_size = 512*MB,
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.boot_flash = 1*MB,
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.user_flash = 64*MB,
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},
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{
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.model = BOARD_MODEL_PRPMC280,
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.variant = 'b',
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.bridge_type = BRIDGE_TYPE_MV64362,
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.subsys0 = 0xff,
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.subsys1 = 0xff,
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.vpd4 = 0x01,
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.vpd4_mask = 0x0f,
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.core_speed = 1*GHz,
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.mem_size = 512*MB,
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.boot_flash = 0,
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.user_flash = 0,
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},
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{
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.model = BOARD_MODEL_PRPMC280,
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.variant = 'c',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xff,
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.subsys1 = 0xff,
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.vpd4 = 0x02,
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.vpd4_mask = 0x0f,
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.core_speed = 733*MHz,
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.mem_size = 512*MB,
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.boot_flash = 1*MB,
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.user_flash = 64*MB,
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},
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{
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.model = BOARD_MODEL_PRPMC280,
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.variant = 'd',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xff,
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.subsys1 = 0xff,
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.vpd4 = 0x03,
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.vpd4_mask = 0x0f,
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.core_speed = 1*GHz,
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.mem_size = 1*GB,
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.boot_flash = 1*MB,
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.user_flash = 64*MB,
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},
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{
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.model = BOARD_MODEL_PRPMC280,
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.variant = 'e',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xff,
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.subsys1 = 0xff,
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.vpd4 = 0x04,
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.vpd4_mask = 0x0f,
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.core_speed = 1*GHz,
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.mem_size = 512*MB,
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.boot_flash = 1*MB,
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.user_flash = 64*MB,
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},
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{
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.model = BOARD_MODEL_PRPMC280,
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.variant = 'f',
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.bridge_type = BRIDGE_TYPE_MV64362,
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.subsys0 = 0xff,
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.subsys1 = 0xff,
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.vpd4 = 0x05,
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.vpd4_mask = 0x0f,
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.core_speed = 733*MHz,
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.mem_size = 128*MB,
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.boot_flash = 1*MB,
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.user_flash = 0,
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},
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{
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.model = BOARD_MODEL_PRPMC280,
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.variant = 'g',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xff,
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.subsys1 = 0xff,
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.vpd4 = 0x06,
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.vpd4_mask = 0x0f,
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.core_speed = 1*GHz,
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.mem_size = 256*MB,
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.boot_flash = 1*MB,
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.user_flash = 0,
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},
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{
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.model = BOARD_MODEL_PRPMC280,
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.variant = 'h',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xff,
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.subsys1 = 0xff,
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.vpd4 = 0x07,
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.vpd4_mask = 0x0f,
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.core_speed = 1*GHz,
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.mem_size = 1*GB,
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.boot_flash = 1*MB,
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.user_flash = 64*MB,
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},
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{
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.model = BOARD_MODEL_PRPMC2800,
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.variant = 'a',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xb2,
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.subsys1 = 0x8c,
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.vpd4 = 0x00,
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.vpd4_mask = 0x00,
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.core_speed = 1*GHz,
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.mem_size = 512*MB,
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.boot_flash = 2*MB,
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.user_flash = 64*MB,
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},
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{
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.model = BOARD_MODEL_PRPMC2800,
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.variant = 'b',
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.bridge_type = BRIDGE_TYPE_MV64362,
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.subsys0 = 0xb2,
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.subsys1 = 0x8d,
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.vpd4 = 0x00,
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.vpd4_mask = 0x00,
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.core_speed = 1*GHz,
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.mem_size = 512*MB,
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.boot_flash = 0,
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.user_flash = 0,
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},
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{
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.model = BOARD_MODEL_PRPMC2800,
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.variant = 'c',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xb2,
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.subsys1 = 0x8e,
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.vpd4 = 0x00,
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.vpd4_mask = 0x00,
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.core_speed = 733*MHz,
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.mem_size = 512*MB,
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.boot_flash = 2*MB,
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.user_flash = 64*MB,
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},
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{
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.model = BOARD_MODEL_PRPMC2800,
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.variant = 'd',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xb2,
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.subsys1 = 0x8f,
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.vpd4 = 0x00,
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.vpd4_mask = 0x00,
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.core_speed = 1*GHz,
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.mem_size = 1*GB,
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.boot_flash = 2*MB,
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.user_flash = 64*MB,
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},
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{
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.model = BOARD_MODEL_PRPMC2800,
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.variant = 'e',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xa2,
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.subsys1 = 0x8a,
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.vpd4 = 0x00,
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.vpd4_mask = 0x00,
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.core_speed = 1*GHz,
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.mem_size = 512*MB,
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.boot_flash = 2*MB,
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.user_flash = 64*MB,
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},
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{
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.model = BOARD_MODEL_PRPMC2800,
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.variant = 'f',
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.bridge_type = BRIDGE_TYPE_MV64362,
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.subsys0 = 0xa2,
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.subsys1 = 0x8b,
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.vpd4 = 0x00,
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.vpd4_mask = 0x00,
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.core_speed = 733*MHz,
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.mem_size = 128*MB,
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.boot_flash = 2*MB,
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.user_flash = 0,
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},
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{
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.model = BOARD_MODEL_PRPMC2800,
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.variant = 'g',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xa2,
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.subsys1 = 0x8c,
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.vpd4 = 0x00,
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.vpd4_mask = 0x00,
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.core_speed = 1*GHz,
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.mem_size = 2*GB,
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.boot_flash = 2*MB,
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.user_flash = 64*MB,
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},
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{
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.model = BOARD_MODEL_PRPMC2800,
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.variant = 'h',
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.bridge_type = BRIDGE_TYPE_MV64360,
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.subsys0 = 0xa2,
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.subsys1 = 0x8d,
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.vpd4 = 0x00,
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.vpd4_mask = 0x00,
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.core_speed = 733*MHz,
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.mem_size = 1*GB,
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.boot_flash = 2*MB,
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.user_flash = 64*MB,
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},
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};
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static struct prpmc2800_board_info *prpmc2800_get_board_info(u8 *vpd)
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{
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struct prpmc2800_board_info *bip;
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int i;
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for (i=0,bip=prpmc2800_board_info; i<ARRAY_SIZE(prpmc2800_board_info);
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i++,bip++)
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if ((vpd[0] == bip->subsys0) && (vpd[1] == bip->subsys1)
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&& ((vpd[4] & bip->vpd4_mask) == bip->vpd4))
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return bip;
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return NULL;
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}
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/* Get VPD from i2c eeprom 2, then match it to a board info entry */
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static struct prpmc2800_board_info *prpmc2800_get_bip(void)
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{
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struct prpmc2800_board_info *bip;
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u8 vpd[5];
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int rc;
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if (mv64x60_i2c_open())
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fatal("Error: Can't open i2c device\n\r");
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/* Get VPD from i2c eeprom-2 */
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memset(vpd, 0, sizeof(vpd));
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rc = mv64x60_i2c_read(EEPROM2_ADDR, vpd, 0x1fde, 2, sizeof(vpd));
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if (rc < 0)
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fatal("Error: Couldn't read eeprom2\n\r");
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mv64x60_i2c_close();
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/* Get board type & related info */
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bip = prpmc2800_get_board_info(vpd);
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if (bip == NULL) {
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printf("Error: Unsupported board or corrupted VPD:\n\r");
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printf(" 0x%x 0x%x 0x%x 0x%x 0x%x\n\r",
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vpd[0], vpd[1], vpd[2], vpd[3], vpd[4]);
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printf("Using device tree defaults...\n\r");
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}
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return bip;
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}
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static void prpmc2800_bridge_setup(u32 mem_size)
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{
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u32 i, v[12], enables, acc_bits;
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u32 pci_base_hi, pci_base_lo, size, buf[2];
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unsigned long cpu_base;
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int rc;
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void *devp;
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u8 *bridge_pbase, is_coherent;
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struct mv64x60_cpu2pci_win *tbl;
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bridge_pbase = mv64x60_get_bridge_pbase();
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is_coherent = mv64x60_is_coherent();
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if (is_coherent)
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acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
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| MV64x60_PCI_ACC_CNTL_SWAP_NONE
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| MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
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| MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
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else
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acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
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| MV64x60_PCI_ACC_CNTL_SWAP_NONE
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| MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
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| MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
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mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
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mv64x60_config_pci_windows(bridge_base, bridge_pbase, 0, 0, mem_size,
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acc_bits);
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/* Get the cpu -> pci i/o & mem mappings from the device tree */
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devp = find_node_by_compatible(NULL, "marvell,mv64360-pci");
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if (devp == NULL)
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fatal("Error: Missing marvell,mv64360-pci"
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" device tree node\n\r");
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rc = getprop(devp, "ranges", v, sizeof(v));
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if (rc != sizeof(v))
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fatal("Error: Can't find marvell,mv64360-pci ranges"
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" property\n\r");
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/* Get the cpu -> pci i/o & mem mappings from the device tree */
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devp = find_node_by_compatible(NULL, "marvell,mv64360");
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if (devp == NULL)
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fatal("Error: Missing marvell,mv64360 device tree node\n\r");
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enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
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enables |= 0x0007fe00; /* Disable all cpu->pci windows */
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out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
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for (i=0; i<12; i+=6) {
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switch (v[i] & 0xff000000) {
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case 0x01000000: /* PCI I/O Space */
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tbl = mv64x60_cpu2pci_io;
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break;
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case 0x02000000: /* PCI MEM Space */
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tbl = mv64x60_cpu2pci_mem;
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break;
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default:
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continue;
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}
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pci_base_hi = v[i+1];
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pci_base_lo = v[i+2];
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cpu_base = v[i+3];
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size = v[i+5];
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buf[0] = cpu_base;
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buf[1] = size;
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if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
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fatal("Error: Can't translate PCI address 0x%x\n\r",
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(u32)cpu_base);
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mv64x60_config_cpu2pci_window(bridge_base, 0, pci_base_hi,
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pci_base_lo, cpu_base, size, tbl);
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}
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enables &= ~0x00000600; /* Enable cpu->pci0 i/o, cpu->pci0 mem0 */
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out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
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}
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static void prpmc2800_fixups(void)
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{
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u32 v[2], l, mem_size;
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int rc;
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void *devp;
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char model[BOARD_MODEL_MAX];
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struct prpmc2800_board_info *bip;
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bip = prpmc2800_get_bip(); /* Get board info based on VPD */
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mem_size = (bip) ? bip->mem_size : mv64x60_get_mem_size(bridge_base);
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prpmc2800_bridge_setup(mem_size); /* Do necessary bridge setup */
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/* If the VPD doesn't match what we know about, just use the
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* defaults already in the device tree.
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*/
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if (!bip)
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return;
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/* Know the board type so override device tree defaults */
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/* Set /model appropriately */
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devp = finddevice("/");
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if (devp == NULL)
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fatal("Error: Missing '/' device tree node\n\r");
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memset(model, 0, BOARD_MODEL_MAX);
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strncpy(model, BOARD_MODEL, BOARD_MODEL_MAX - 2);
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l = strlen(model);
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if (bip->model == BOARD_MODEL_PRPMC280)
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l--;
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model[l++] = bip->variant;
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model[l++] = '\0';
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setprop(devp, "model", model, l);
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/* Set /cpus/PowerPC,7447/clock-frequency */
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devp = find_node_by_prop_value_str(NULL, "device_type", "cpu");
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if (devp == NULL)
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fatal("Error: Missing proper cpu device tree node\n\r");
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v[0] = bip->core_speed;
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setprop(devp, "clock-frequency", &v[0], sizeof(v[0]));
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/* Set /memory/reg size */
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devp = finddevice("/memory");
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if (devp == NULL)
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fatal("Error: Missing /memory device tree node\n\r");
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v[0] = 0;
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v[1] = bip->mem_size;
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setprop(devp, "reg", v, sizeof(v));
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/* Update model, if this is a mv64362 */
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if (bip->bridge_type == BRIDGE_TYPE_MV64362) {
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devp = find_node_by_compatible(NULL, "marvell,mv64360");
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if (devp == NULL)
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fatal("Error: Missing marvell,mv64360"
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" device tree node\n\r");
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setprop(devp, "model", "mv64362", strlen("mv64362") + 1);
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}
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/* Set User FLASH size */
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devp = find_node_by_compatible(NULL, "direct-mapped");
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if (devp == NULL)
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fatal("Error: Missing User FLASH device tree node\n\r");
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rc = getprop(devp, "reg", v, sizeof(v));
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if (rc != sizeof(v))
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fatal("Error: Can't find User FLASH reg property\n\r");
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v[1] = bip->user_flash;
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setprop(devp, "reg", v, sizeof(v));
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}
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#define MV64x60_MPP_CNTL_0 0xf000
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#define MV64x60_MPP_CNTL_2 0xf008
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#define MV64x60_GPP_IO_CNTL 0xf100
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#define MV64x60_GPP_LEVEL_CNTL 0xf110
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#define MV64x60_GPP_VALUE_SET 0xf118
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static void prpmc2800_reset(void)
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{
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u32 temp;
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udelay(5000000);
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if (bridge_base != 0) {
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temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
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temp &= 0xFFFF0FFF;
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out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
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temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
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temp |= 0x00000004;
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out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
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temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
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temp |= 0x00000004;
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out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
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temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
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temp &= 0xFFFF0FFF;
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out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
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temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
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temp |= 0x00080000;
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out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
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temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
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temp |= 0x00080000;
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out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
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out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
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0x00080004);
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}
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for (;;);
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}
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#define HEAP_SIZE (16*MB)
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static struct gunzip_state gzstate;
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void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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struct elf_info ei;
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char *heap_start, *dtb;
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int dt_size = _dtb_end - _dtb_start;
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void *vmlinuz_addr = _vmlinux_start;
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unsigned long vmlinuz_size = _vmlinux_end - _vmlinux_start;
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char elfheader[256];
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if (dt_size <= 0) /* No fdt */
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exit();
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/*
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* Start heap after end of the kernel (after decompressed to
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* address 0) or the end of the zImage, whichever is higher.
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* That's so things allocated by simple_alloc won't overwrite
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* any part of the zImage and the kernel won't overwrite the dtb
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* when decompressed & relocated.
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*/
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gunzip_start(&gzstate, vmlinuz_addr, vmlinuz_size);
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gunzip_exactly(&gzstate, elfheader, sizeof(elfheader));
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if (!parse_elf32(elfheader, &ei))
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exit();
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heap_start = (char *)(ei.memsize + ei.elfoffset); /* end of kernel*/
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heap_start = max(heap_start, (char *)_end); /* end of zImage */
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if ((unsigned)simple_alloc_init(heap_start, HEAP_SIZE, 2*KB, 16)
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> (128*MB))
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exit();
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/* Relocate dtb to safe area past end of zImage & kernel */
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dtb = malloc(dt_size);
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if (!dtb)
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exit();
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memmove(dtb, _dtb_start, dt_size);
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fdt_init(dtb);
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bridge_base = mv64x60_get_bridge_base();
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platform_ops.fixups = prpmc2800_fixups;
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platform_ops.exit = prpmc2800_reset;
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if (serial_console_init() < 0)
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exit();
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}
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/* _zimage_start called very early--need to turn off external interrupts */
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asm (" .globl _zimage_start\n\
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_zimage_start:\n\
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mfmsr 10\n\
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rlwinm 10,10,0,~(1<<15) /* Clear MSR_EE */\n\
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sync\n\
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mtmsr 10\n\
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isync\n\
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b _zimage_start_lib\n\
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");
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