62ec0b9754
The CEC 32K AO Clock is a dual divider with dual counter to provide a more precise 32768Hz clock for the CEC subsystem from the external xtal. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
43 lines
964 B
C
43 lines
964 B
C
/*
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* Copyright (c) 2017 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __GXBB_AOCLKC_H
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#define __GXBB_AOCLKC_H
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/* AO Configuration Clock registers offsets */
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#define AO_RTI_PWR_CNTL_REG1 0x0c
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#define AO_RTI_PWR_CNTL_REG0 0x10
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#define AO_RTI_GEN_CNTL_REG0 0x40
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#define AO_OSCIN_CNTL 0x58
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#define AO_CRT_CLK_CNTL1 0x68
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#define AO_RTC_ALT_CLK_CNTL0 0x94
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#define AO_RTC_ALT_CLK_CNTL1 0x98
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struct aoclk_gate_regmap {
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struct clk_hw hw;
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unsigned bit_idx;
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struct regmap *regmap;
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spinlock_t *lock;
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};
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#define to_aoclk_gate_regmap(_hw) \
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container_of(_hw, struct aoclk_gate_regmap, hw)
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extern const struct clk_ops meson_aoclk_gate_regmap_ops;
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struct aoclk_cec_32k {
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struct clk_hw hw;
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struct regmap *regmap;
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spinlock_t *lock;
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};
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#define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw)
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extern const struct clk_ops meson_aoclk_cec_32k_ops;
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#endif /* __GXBB_AOCLKC_H */
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