53492b1de4
This adds hugetlbfs support on System z, using both hardware large page support if available and software large page emulation on older hardware. Shared (large) page tables are implemented in software emulation mode, by using page->index of the first tail page from a compound large page to store page table information. Signed-off-by: Gerald Schaefer <geraldsc@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
200 lines
5.2 KiB
ArmAsm
200 lines
5.2 KiB
ArmAsm
/*
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* arch/s390/kernel/head64.S
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*
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* Copyright (C) IBM Corp. 1999,2006
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*
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* Author(s): Hartmut Penner <hp@de.ibm.com>
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* Martin Schwidefsky <schwidefsky@de.ibm.com>
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* Rob van der Heij <rvdhei@iae.nl>
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* Heiko Carstens <heiko.carstens@de.ibm.com>
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*
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*/
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#
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# startup-code at 0x10000, running in absolute addressing mode
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# this is called either by the ipl loader or directly by PSW restart
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# or linload or SALIPL
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#
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.org 0x10000
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startup:basr %r13,0 # get base
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.LPG0: l %r13,0f-.LPG0(%r13)
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b 0(%r13)
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0: .long startup_continue
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#
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# params at 10400 (setup.h)
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#
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.org PARMAREA
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.quad 0 # IPL_DEVICE
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.quad 0 # INITRD_START
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.quad 0 # INITRD_SIZE
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.org COMMAND_LINE
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.byte "root=/dev/ram0 ro"
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.byte 0
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.org 0x11000
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startup_continue:
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basr %r13,0 # get base
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.LPG1: sll %r13,1 # remove high order bit
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srl %r13,1
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#ifdef CONFIG_ZFCPDUMP
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# check if we have been ipled using zfcp dump:
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tm 0xb9,0x01 # test if subchannel is enabled
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jno .nodump # subchannel disabled
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l %r1,0xb8
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la %r5,.Lipl_schib-.LPG1(%r13)
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stsch 0(%r5) # get schib of subchannel
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jne .nodump # schib not available
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tm 5(%r5),0x01 # devno valid?
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jno .nodump
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tm 4(%r5),0x80 # qdio capable device?
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jno .nodump
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l %r2,20(%r0) # address of ipl parameter block
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lhi %r3,0
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ic %r3,0x148(%r2) # get opt field
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chi %r3,0x20 # load with dump?
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jne .nodump
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# store all prefix registers in case of load with dump:
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la %r7,0 # base register for 0 page
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la %r8,0 # first cpu
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l %r11,.Lpref_arr_ptr-.LPG1(%r13) # address of prefix array
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ahi %r11,4 # skip boot cpu
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lr %r12,%r11
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ahi %r12,(CONFIG_NR_CPUS*4) # end of prefix array
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stap .Lcurrent_cpu+2-.LPG1(%r13) # store current cpu addr
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1:
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cl %r8,.Lcurrent_cpu-.LPG1(%r13) # is ipl cpu ?
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je 4f # if yes get next cpu
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2:
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lr %r9,%r7
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sigp %r9,%r8,0x9 # stop & store status of cpu
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brc 8,3f # accepted
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brc 4,4f # status stored: next cpu
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brc 2,2b # busy: try again
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brc 1,4f # not op: next cpu
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3:
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mvc 0(4,%r11),264(%r7) # copy prefix register to prefix array
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ahi %r11,4 # next element in prefix array
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clr %r11,%r12
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je 5f # no more space in prefix array
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4:
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ahi %r8,1 # next cpu (r8 += 1)
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cl %r8,.Llast_cpu-.LPG1(%r13) # is last possible cpu ?
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jl 1b # jump if not last cpu
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5:
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lhi %r1,2 # mode 2 = esame (dump)
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j 6f
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.align 4
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.Lipl_schib:
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.rept 13
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.long 0
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.endr
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.nodump:
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lhi %r1,1 # mode 1 = esame (normal ipl)
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6:
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#else
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lhi %r1,1 # mode 1 = esame (normal ipl)
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#endif /* CONFIG_ZFCPDUMP */
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mvi __LC_AR_MODE_ID,1 # set esame flag
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slr %r0,%r0 # set cpuid to zero
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sigp %r1,%r0,0x12 # switch to esame mode
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sam64 # switch to 64 bit mode
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lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
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lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
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# move IPL device to lowcore
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mvc __LC_IPLDEV(4),IPL_DEVICE+4-PARMAREA(%r12)
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#
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# Setup stack
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#
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larl %r15,init_thread_union
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lg %r14,__TI_task(%r15) # cache current in lowcore
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stg %r14,__LC_CURRENT
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aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
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stg %r15,__LC_KERNEL_STACK # set end of kernel stack
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aghi %r15,-160
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xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) # clear backchain
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#
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# Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
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# and create a kernel NSS if the SAVESYS= parm is defined
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#
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brasl %r14,startup_init
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lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
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# virtual and never return ...
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.align 16
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.Lentry:.quad 0x0000000180000000,_stext
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.Lctl: .quad 0x04350002 # cr0: various things
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.quad 0 # cr1: primary space segment table
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.quad .Lduct # cr2: dispatchable unit control table
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.quad 0 # cr3: instruction authorization
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.quad 0 # cr4: instruction authorization
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.quad .Lduct # cr5: primary-aste origin
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.quad 0 # cr6: I/O interrupts
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.quad 0 # cr7: secondary space segment table
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.quad 0 # cr8: access registers translation
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.quad 0 # cr9: tracing off
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.quad 0 # cr10: tracing off
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.quad 0 # cr11: tracing off
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.quad 0 # cr12: tracing off
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.quad 0 # cr13: home space segment table
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.quad 0xc0000000 # cr14: machine check handling off
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.quad 0 # cr15: linkage stack operations
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.Lpcmsk:.quad 0x0000000180000000
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.L4malign:.quad 0xffffffffffc00000
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.Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
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.Lnop: .long 0x07000700
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#ifdef CONFIG_ZFCPDUMP
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.Lcurrent_cpu:
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.long 0x0
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.Llast_cpu:
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.long 0x0000ffff
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.Lpref_arr_ptr:
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.long zfcpdump_prefix_array
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#endif /* CONFIG_ZFCPDUMP */
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.Lparmaddr:
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.quad PARMAREA
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.align 64
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.Lduct: .long 0,0,0,0,.Lduald,0,0,0
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.long 0,0,0,0,0,0,0,0
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.align 128
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.Lduald:.rept 8
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.long 0x80000000,0,0,0 # invalid access-list entries
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.endr
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.org 0x12000
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.globl _ehead
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_ehead:
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#ifdef CONFIG_SHARED_KERNEL
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.org 0x100000
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#endif
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#
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# startup-code, running in absolute addressing mode
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#
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.globl _stext
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_stext: basr %r13,0 # get base
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.LPG3:
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# check control registers
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stctg %c0,%c15,0(%r15)
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oi 6(%r15),0x40 # enable sigp emergency signal
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oi 4(%r15),0x10 # switch on low address proctection
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lctlg %c0,%c15,0(%r15)
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lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess
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brasl %r14,start_kernel # go to C code
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#
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# We returned from start_kernel ?!? PANIK
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#
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basr %r13,0
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lpswe .Ldw-.(%r13) # load disabled wait psw
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.align 8
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.Ldw: .quad 0x0002000180000000,0x0000000000000000
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.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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