Graf Yang 5bc6e3cfe6 Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions ... The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM regions. Any code that attempted to use these would wrongly crash due to a CPLB miss. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>		2009-07-16 01:52:51 -04:00
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cacheinit.c	Blackfin: add workaround for anomaly 05000287	2009-06-12 06:11:39 -04:00
cplbinit.c	Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions	2009-07-16 01:52:51 -04:00
cplbmgr.c	Blackfin: only handle CPLB protection violations when MPU is enabled	2009-06-13 07:20:06 -04:00
Makefile	Blackfin arch: Faster C implementation of no-MPU CPLB handler	2009-01-07 23:14:38 +08:00