ec971c91c5
This currently happens for 'drivers/input/touch/mainstone-wm97xx.c'. Signed-off-by: Eric Miao <eric.miao@marvell.com>
102 lines
4.4 KiB
C
102 lines
4.4 KiB
C
#ifndef __ASM_ARCH_REGS_AC97_H
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#define __ASM_ARCH_REGS_AC97_H
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#include <mach/hardware.h>
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/*
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* AC97 Controller registers
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*/
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#define POCR __REG(0x40500000) /* PCM Out Control Register */
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#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
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#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define PICR __REG(0x40500004) /* PCM In Control Register */
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#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
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#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define MCCR __REG(0x40500008) /* Mic In Control Register */
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#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
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#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define GCR __REG(0x4050000C) /* Global Control Register */
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#ifdef CONFIG_PXA3xx
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#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
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#endif
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#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
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#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
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#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
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#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
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#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
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#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
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#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
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#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
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#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
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#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
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#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
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#define POSR __REG(0x40500010) /* PCM Out Status Register */
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#define POSR_FIFOE (1 << 4) /* FIFO error */
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#define POSR_FSR (1 << 2) /* FIFO Service Request */
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#define PISR __REG(0x40500014) /* PCM In Status Register */
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#define PISR_FIFOE (1 << 4) /* FIFO error */
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#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
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#define PISR_FSR (1 << 2) /* FIFO Service Request */
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#define MCSR __REG(0x40500018) /* Mic In Status Register */
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#define MCSR_FIFOE (1 << 4) /* FIFO error */
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#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
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#define MCSR_FSR (1 << 2) /* FIFO Service Request */
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#define GSR __REG(0x4050001C) /* Global Status Register */
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#define GSR_CDONE (1 << 19) /* Command Done */
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#define GSR_SDONE (1 << 18) /* Status Done */
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#define GSR_RDCS (1 << 15) /* Read Completion Status */
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#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
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#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
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#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
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#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
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#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
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#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
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#define GSR_PCR (1 << 8) /* Primary Codec Ready */
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#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
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#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
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#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
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#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
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#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
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#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
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#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
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#define CAR __REG(0x40500020) /* CODEC Access Register */
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#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
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#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
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#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
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#define MOCR __REG(0x40500100) /* Modem Out Control Register */
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#define MOCR_FEIE (1 << 3) /* FIFO Error */
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#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define MICR __REG(0x40500108) /* Modem In Control Register */
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#define MICR_FEIE (1 << 3) /* FIFO Error */
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#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define MOSR __REG(0x40500110) /* Modem Out Status Register */
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#define MOSR_FIFOE (1 << 4) /* FIFO error */
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#define MOSR_FSR (1 << 2) /* FIFO Service Request */
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#define MISR __REG(0x40500118) /* Modem In Status Register */
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#define MISR_FIFOE (1 << 4) /* FIFO error */
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#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
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#define MISR_FSR (1 << 2) /* FIFO Service Request */
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#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
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#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
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#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
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#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
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#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
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#endif /* __ASM_ARCH_REGS_AC97_H */
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