b274776c54
A large number of cleanups, all over the platforms. This is dominated largely by the Samsung platforms (s3c, s5p, exynos) and a few of the others moving code out of arch/arm into more appropriate subsystems. The clocksource and irqchip drivers are now abstracted to the point where platforms that are already cleaned up do not need to even specify the driver they use, it can all get configured from the device tree as we do for normal device drivers. The clocksource changes basically touch every single platform in the process. We further clean up the use of platform specific header files here, with the goal of turning more of the platforms over to being "multiplatform" enabled, which implies that they cannot expose their headers to architecture independent code any more. It is expected that no functional changes are part of the cleanup. The overall reduction in total code lines is mostly the result of removing broken and obsolete code. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUSUyKmCrR//JCVInAQIN8RAAnb/uPytmlMjn5yCksF4Mvb/FVbn/TVwz KRIGpCHOzyKK1q7pM8NRUVWfjW2SZqbXJFqx6zBGKSlDPvFTOhsLyyupU+Tnyu5W IX4eIUBwb+a6H7XDHw0X2YI8uHzi5RNLhne0A1QyDKcnuHs1LDAttXnJHaK4Ap6Y NN2YFt3l3ld7DXWXJtMsw5v8lC10aeIFGTvXefaPDAdeMLivmI57qEUMDXknNr7W Odz/Rc0/cw3BNBVl/zNHA0jw7FOjKAymCYYNUa4xDCJEr+JnIRTqizd0N/YIIC7x aA2xjJ3oKUFyF51yiJE6nFuTyJznhwtehc+uiMOSIkjrPLym52LEHmd7G5Yqlmjz oiei09qBb870q3lGxwfht9iaeIwYgQFYGfD0yW5QWArCO5pxhtCPLPH7YZNZtcQd ZJRSGGqT/ljBz3bm0K9OLESeeTTN7+Nxvtpiz/CD+Piegz0gWJzDYJRTzkJ3UWpA WTVhVQdWUeX2JrNkgM7Z3Tu8iXOe+LIEs7kVXGJZSREmIIZiRvR36UrODZtAkp9I 7YQ+srX/uaR832pgK0RrHK0zY0psU6MmIvhYxJZFbx7keiPA9eH6drb0x7tGqcUD FzEUzvcZvyqppndfBi+R60H/YKAhJDEXdwxzo6dyCpPQaW1T9GnzIqXuE1zin+Aw X7Y8YywMbHI= =DvgJ -----END PGP SIGNATURE----- Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Arnd Bergmann: "A large number of cleanups, all over the platforms. This is dominated largely by the Samsung platforms (s3c, s5p, exynos) and a few of the others moving code out of arch/arm into more appropriate subsystems. The clocksource and irqchip drivers are now abstracted to the point where platforms that are already cleaned up do not need to even specify the driver they use, it can all get configured from the device tree as we do for normal device drivers. The clocksource changes basically touch every single platform in the process. We further clean up the use of platform specific header files here, with the goal of turning more of the platforms over to being "multiplatform" enabled, which implies that they cannot expose their headers to architecture independent code any more. It is expected that no functional changes are part of the cleanup. The overall reduction in total code lines is mostly the result of removing broken and obsolete code." * tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (133 commits) ARM: mvebu: correct gated clock documentation ARM: kirkwood: add missing include for nsa310 ARM: exynos: move exynos4210-combiner to drivers/irqchip mfd: db8500-prcmu: update resource passing drivers/db8500-cpufreq: delete dangling include ARM: at91: remove NEOCORE 926 board sunxi: Cleanup the reset code and add meaningful registers defines ARM: S3C24XX: header mach/regs-mem.h local ARM: S3C24XX: header mach/regs-power.h local ARM: S3C24XX: header mach/regs-s3c2412-mem.h local ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/ ARM: S3C24XX: transform s3c2443 subirqs into new structure ARM: S3C24XX: modify s3c2443 irq init to initialize all irqs ARM: S3C24XX: move s3c2443 irq code to irq.c ARM: S3C24XX: transform s3c2416 irqs into new structure ARM: S3C24XX: modify s3c2416 irq init to initialize all irqs ARM: S3C24XX: move s3c2416 irq init to common irq code ARM: S3C24XX: Modify s3c_irq_wake to use the hwirq property ARM: S3C24XX: Move irq syscore-ops to irq-pm clocksource: always define CLOCKSOURCE_OF_DECLARE ...
432 lines
10 KiB
C
432 lines
10 KiB
C
/*
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* Copyright (c) 2005-2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <linux/device.h>
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#include <linux/syscore_ops.h>
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#include <linux/serial_core.h>
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#include <linux/clk.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/i2c/tps65010.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <linux/platform_data/mtd-nand-s3c2410.h>
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#include <linux/platform_data/i2c-s3c2410.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq.h>
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#include <plat/devs.h>
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#include <plat/gpio-cfg.h>
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#include <plat/regs-serial.h>
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#include <mach/hardware.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-lcd.h>
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#include "common.h"
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#include "osiris.h"
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#include "regs-mem.h"
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/* onboard perihperal map */
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static struct map_desc osiris_iodesc[] __initdata = {
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/* ISA IO areas (may be over-written later) */
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{
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.virtual = (u32)S3C24XX_VA_ISA_BYTE,
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.pfn = __phys_to_pfn(S3C2410_CS5),
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.length = SZ_16M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = __phys_to_pfn(S3C2410_CS5),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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/* CPLD control registers */
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{
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.virtual = (u32)OSIRIS_VA_CTRL0,
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.pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)OSIRIS_VA_CTRL1,
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.pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)OSIRIS_VA_CTRL2,
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.pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)OSIRIS_VA_IDREG,
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.pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
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.length = SZ_16K,
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.type = MT_DEVICE,
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},
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};
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#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
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#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
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#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
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static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
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},
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
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}
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};
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/* NAND Flash on Osiris board */
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static int external_map[] = { 2 };
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static int chip0_map[] = { 0 };
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static int chip1_map[] = { 1 };
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static struct mtd_partition __initdata osiris_default_nand_part[] = {
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[0] = {
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.name = "Boot Agent",
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.size = SZ_16K,
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.offset = 0,
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},
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[1] = {
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.name = "/boot",
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.size = SZ_4M - SZ_16K,
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.offset = SZ_16K,
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},
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[2] = {
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.name = "user1",
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.offset = SZ_4M,
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.size = SZ_32M - SZ_4M,
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},
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[3] = {
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.name = "user2",
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.offset = SZ_32M,
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.size = MTDPART_SIZ_FULL,
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}
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};
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static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
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[0] = {
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.name = "Boot Agent",
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.size = SZ_128K,
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.offset = 0,
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},
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[1] = {
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.name = "/boot",
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.size = SZ_4M - SZ_128K,
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.offset = SZ_128K,
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},
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[2] = {
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.name = "user1",
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.offset = SZ_4M,
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.size = SZ_32M - SZ_4M,
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},
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[3] = {
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.name = "user2",
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.offset = SZ_32M,
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.size = MTDPART_SIZ_FULL,
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}
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};
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/* the Osiris has 3 selectable slots for nand-flash, the two
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* on-board chip areas, as well as the external slot.
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*
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* Note, there is no current hot-plug support for the External
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* socket.
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*/
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static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
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[1] = {
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.name = "External",
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.nr_chips = 1,
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.nr_map = external_map,
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.options = NAND_SCAN_SILENT_NODEV,
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.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
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.partitions = osiris_default_nand_part,
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},
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[0] = {
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.name = "chip0",
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.nr_chips = 1,
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.nr_map = chip0_map,
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.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
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.partitions = osiris_default_nand_part,
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},
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[2] = {
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.name = "chip1",
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.nr_chips = 1,
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.nr_map = chip1_map,
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.options = NAND_SCAN_SILENT_NODEV,
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.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
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.partitions = osiris_default_nand_part,
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},
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};
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static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
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{
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unsigned int tmp;
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slot = set->nr_map[slot] & 3;
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pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
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slot, set, set->nr_map);
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tmp = __raw_readb(OSIRIS_VA_CTRL0);
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tmp &= ~OSIRIS_CTRL0_NANDSEL;
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tmp |= slot;
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pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
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__raw_writeb(tmp, OSIRIS_VA_CTRL0);
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}
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static struct s3c2410_platform_nand __initdata osiris_nand_info = {
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.tacls = 25,
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.twrph0 = 60,
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.twrph1 = 60,
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.nr_sets = ARRAY_SIZE(osiris_nand_sets),
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.sets = osiris_nand_sets,
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.select_chip = osiris_nand_select,
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};
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/* PCMCIA control and configuration */
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static struct resource osiris_pcmcia_resource[] = {
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[0] = DEFINE_RES_MEM(0x0f000000, SZ_1M),
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[1] = DEFINE_RES_MEM(0x0c000000, SZ_1M),
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};
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static struct platform_device osiris_pcmcia = {
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.name = "osiris-pcmcia",
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.id = -1,
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.num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
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.resource = osiris_pcmcia_resource,
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};
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/* Osiris power management device */
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#ifdef CONFIG_PM
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static unsigned char pm_osiris_ctrl0;
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static int osiris_pm_suspend(void)
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{
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unsigned int tmp;
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pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
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tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
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/* ensure correct NAND slot is selected on resume */
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if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
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tmp |= 2;
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__raw_writeb(tmp, OSIRIS_VA_CTRL0);
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/* ensure that an nRESET is not generated on resume. */
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gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
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gpio_free(S3C2410_GPA(21));
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return 0;
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}
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static void osiris_pm_resume(void)
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{
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if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
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__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
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__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
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s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
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}
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#else
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#define osiris_pm_suspend NULL
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#define osiris_pm_resume NULL
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#endif
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static struct syscore_ops osiris_pm_syscore_ops = {
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.suspend = osiris_pm_suspend,
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.resume = osiris_pm_resume,
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};
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/* Link for DVS driver to TPS65011 */
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static void osiris_tps_release(struct device *dev)
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{
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/* static device, do not need to release anything */
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}
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static struct platform_device osiris_tps_device = {
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.name = "osiris-dvs",
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.id = -1,
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.dev.release = osiris_tps_release,
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};
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static int osiris_tps_setup(struct i2c_client *client, void *context)
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{
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osiris_tps_device.dev.parent = &client->dev;
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return platform_device_register(&osiris_tps_device);
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}
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static int osiris_tps_remove(struct i2c_client *client, void *context)
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{
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platform_device_unregister(&osiris_tps_device);
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return 0;
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}
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static struct tps65010_board osiris_tps_board = {
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.base = -1, /* GPIO can go anywhere at the moment */
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.setup = osiris_tps_setup,
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.teardown = osiris_tps_remove,
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};
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/* I2C devices fitted. */
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static struct i2c_board_info osiris_i2c_devs[] __initdata = {
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{
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I2C_BOARD_INFO("tps65011", 0x48),
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.irq = IRQ_EINT20,
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.platform_data = &osiris_tps_board,
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},
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};
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/* Standard Osiris devices */
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static struct platform_device *osiris_devices[] __initdata = {
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&s3c_device_i2c0,
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&s3c_device_wdt,
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&s3c_device_nand,
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&osiris_pcmcia,
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};
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static struct clk *osiris_clocks[] __initdata = {
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&s3c24xx_dclk0,
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&s3c24xx_dclk1,
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&s3c24xx_clkout0,
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&s3c24xx_clkout1,
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&s3c24xx_uclk,
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};
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static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
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.refresh = 7800, /* refresh period is 7.8usec */
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.auto_io = 1,
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.need_io = 1,
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};
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static void __init osiris_map_io(void)
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{
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unsigned long flags;
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/* initialise the clocks */
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s3c24xx_dclk0.parent = &clk_upll;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk1.parent = &clk_upll;
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s3c24xx_dclk1.rate = 24*1000*1000;
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s3c24xx_clkout0.parent = &s3c24xx_dclk0;
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s3c24xx_clkout1.parent = &s3c24xx_dclk1;
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s3c24xx_uclk.parent = &s3c24xx_clkout1;
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s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
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s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
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s3c24xx_init_clocks(0);
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s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
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/* check for the newer revision boards with large page nand */
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if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
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printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
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__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
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osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
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osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
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} else {
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/* write-protect line to the NAND */
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gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
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gpio_free(S3C2410_GPA(0));
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}
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/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
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|
|
|
local_irq_save(flags);
|
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__raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
|
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local_irq_restore(flags);
|
|
}
|
|
|
|
static void __init osiris_init(void)
|
|
{
|
|
register_syscore_ops(&osiris_pm_syscore_ops);
|
|
|
|
s3c_i2c0_set_platdata(NULL);
|
|
s3c_nand_set_platdata(&osiris_nand_info);
|
|
|
|
s3c_cpufreq_setboard(&osiris_cpufreq);
|
|
|
|
i2c_register_board_info(0, osiris_i2c_devs,
|
|
ARRAY_SIZE(osiris_i2c_devs));
|
|
|
|
platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
|
|
};
|
|
|
|
MACHINE_START(OSIRIS, "Simtec-OSIRIS")
|
|
/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
|
|
.atag_offset = 0x100,
|
|
.map_io = osiris_map_io,
|
|
.init_irq = s3c24xx_init_irq,
|
|
.init_machine = osiris_init,
|
|
.init_time = s3c24xx_timer_init,
|
|
.restart = s3c244x_restart,
|
|
MACHINE_END
|