3c1a884436
source clock need an independent cg to control, when doing clk mode switch, need gate source clock to avoid hw issue(multi-bit sync hw hang) Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Tested-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
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