a741e67969
The current tlb flush code on powerpc 64 bits has a subtle race since we lost the page table lock due to the possible faulting in of new PTEs after a previous one has been removed but before the corresponding hash entry has been evicted, which can leads to all sort of fatal problems. This patch reworks the batch code completely. It doesn't use the mmu_gather stuff anymore. Instead, we use the lazy mmu hooks that were added by the paravirt code. They have the nice property that the enter/leave lazy mmu mode pair is always fully contained by the PTE lock for a given range of PTEs. Thus we can guarantee that all batches are flushed on a given CPU before it drops that lock. We also generalize batching for any PTE update that require a flush. Batching is now enabled on a CPU by arch_enter_lazy_mmu_mode() and disabled by arch_leave_lazy_mmu_mode(). The code epects that this is always contained within a PTE lock section so no preemption can happen and no PTE insertion in that range from another CPU. When batching is enabled on a CPU, every PTE updates that need a hash flush will use the batch for that flush. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
71 lines
1.6 KiB
C
71 lines
1.6 KiB
C
/*
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* TLB shootdown specifics for powerpc
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*
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* Copyright (C) 2002 Anton Blanchard, IBM Corp.
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* Copyright (C) 2002 Paul Mackerras, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_TLB_H
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#define _ASM_POWERPC_TLB_H
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#ifdef __KERNEL__
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#ifndef __powerpc64__
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#include <asm/pgtable.h>
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#endif
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#ifndef __powerpc64__
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#include <asm/page.h>
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#include <asm/mmu.h>
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#endif
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struct mmu_gather;
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#define tlb_start_vma(tlb, vma) do { } while (0)
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#define tlb_end_vma(tlb, vma) do { } while (0)
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#if !defined(CONFIG_PPC_STD_MMU)
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#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
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#elif defined(__powerpc64__)
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extern void pte_free_finish(void);
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static inline void tlb_flush(struct mmu_gather *tlb)
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{
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pte_free_finish();
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}
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#else
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extern void tlb_flush(struct mmu_gather *tlb);
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#endif
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/* Get the generic bits... */
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#include <asm-generic/tlb.h>
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#if !defined(CONFIG_PPC_STD_MMU) || defined(__powerpc64__)
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#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
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#else
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extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
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unsigned long address);
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static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
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unsigned long address)
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{
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if (pte_val(*ptep) & _PAGE_HASHPTE)
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flush_hash_entry(tlb->mm, ptep, address);
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}
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#endif
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#endif /* __KERNEL__ */
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#endif /* __ASM_POWERPC_TLB_H */
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