7549423000
Patch from Nicolas Pitre This patch provides a new implementation for optimized memory copy functions on ARM. It is made of two levels: a template that consists of the core copy code and separate files that define macros to be used with the core code depending on the type of copy needed. This allows for best performances while sharing the same core for implementing memcpy(), copy_from_user() and copy_to_user() for instance. Two reasons for this work: 1) the current copy_to_user/copy_from_user implementation assumes no task switch will ever occur in the middle of each copied page making it completely unsafe with CONFIG_PREEMPT=y. 2) current copy implementations are measurably suboptimal and optimizing different implementations separately is a pain and more opportunities for bugs. The reason for (1) is the fact that copy inside user pages are performed with the ldm instruction which has no mean for testing user protections and could possibly race with process preemption bypassing the COW mechanism for example. This is a longstanding issue that we said ought to be fixed for about two years now. The solution is to substitute those ldm insns with a series of ldrt or strt insns to enforce user memory protection. At least on StrongARM and XScale cores the ldm is not faster than the equivalent ldr/str insns with a warm i-cache so there is no measurable performance degradation with that change. The fact that the copy code is a template makes it pretty easy to reuse the same core code as for memcpy and benefit from the same performance optimizations. Now (2) is best demonstrated with actual throughput measurements. First, here is a summary of memcopy tests performed on a StrongARM core: PTR alignment buffer size kernel version this version ------------------------------------------------------------ aligned 32 59.73 107.43 unaligned 32 61.31 74.72 aligned 100 132.47 136.15 unaligned 100 103.84 123.76 aligned 4096 130.67 130.80 unaligned 4096 130.68 130.64 aligned 1048576 68.03 68.18 unaligned 1048576 68.03 68.18 The buffer size is in bytes and the measured speed in MB/s. The copy was performed repeatedly with given buffer and throughput averaged over 3 seconds. Here we can see that the current kernel version has a higher entry cost that shows up with small buffers. As buffer size grows both implementation converge to the same throughput. Now here's the exact same test performed on an XScale core (PXA255): PTR alignment buffer size kernel version this version ------------------------------------------------------------ aligned 32 46.99 77.58 unaligned 32 53.61 59.59 aligned 100 107.19 136.59 unaligned 100 83.61 97.58 aligned 4096 129.13 129.98 unaligned 4096 128.36 128.53 aligned 1048576 53.76 59.41 unaligned 1048576 33.67 56.96 Again we can see the entry setup cost being higher for the current kernel before getting to the main copy loop. Then throughput results converge as long as the buffer remains in the cache. Then the 1MB case shows more differences probably due to better pld placement and/or less instruction interlocks in this proposed implementation. Disclaimer: The PXA system was running with slower clocks than the StrongARM system so trying to infer any conclusion by comparing those separate sets of results side by side would be completely inappropriate. So... What this patch does is to replace both memcpy and memmove with an implementation based on the provided copy code template. The memmove code is kept separate since it is used only if the memory areas involved do overlap in which case the code is a transposition of the template but with the copy occurring in the opposite direction (trying to fit that mode into the template turned it into a mess not worth it for memmove alone). And obviously both memcpy and memmove were tested with all kinds of pointer alignments and buffer sizes to exercise all code paths for correctness. The next patch will provide the now trivial replacement implementation copy_to_user and copy_from_user. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
207 lines
4.2 KiB
ArmAsm
207 lines
4.2 KiB
ArmAsm
/*
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* linux/arch/arm/lib/memmove.S
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*
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* Author: Nicolas Pitre
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* Created: Sep 28, 2005
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* Copyright: (C) MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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/*
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* This can be used to enable code to cacheline align the source pointer.
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* Experiments on tested architectures (StrongARM and XScale) didn't show
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* this a worthwhile thing to do. That might be different in the future.
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*/
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//#define CALGN(code...) code
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#define CALGN(code...)
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.text
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/*
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* Prototype: void *memmove(void *dest, const void *src, size_t n);
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*
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* Note:
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*
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* If the memory regions don't overlap, we simply branch to memcpy which is
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* normally a bit faster. Otherwise the copy is done going downwards. This
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* is a transposition of the code from copy_template.S but with the copy
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* occurring in the opposite direction.
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*/
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ENTRY(memmove)
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subs ip, r0, r1
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cmphi r2, ip
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bls memcpy
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stmfd sp!, {r0, r4, lr}
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add r1, r1, r2
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add r0, r0, r2
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subs r2, r2, #4
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blt 8f
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ands ip, r0, #3
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PLD( pld [r1, #-4] )
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bne 9f
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ands ip, r1, #3
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bne 10f
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1: subs r2, r2, #(28)
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stmfd sp!, {r5 - r8}
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blt 5f
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CALGN( ands ip, r1, #31 )
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CALGN( sbcnes r4, ip, r2 ) @ C is always set here
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CALGN( bcs 2f )
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CALGN( adr r4, 6f )
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CALGN( subs r2, r2, ip ) @ C is set here
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CALGN( add pc, r4, ip )
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PLD( pld [r1, #-4] )
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2: PLD( subs r2, r2, #96 )
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PLD( pld [r1, #-32] )
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PLD( blt 4f )
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PLD( pld [r1, #-64] )
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PLD( pld [r1, #-96] )
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3: PLD( pld [r1, #-128] )
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4: ldmdb r1!, {r3, r4, r5, r6, r7, r8, ip, lr}
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subs r2, r2, #32
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stmdb r0!, {r3, r4, r5, r6, r7, r8, ip, lr}
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bge 3b
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PLD( cmn r2, #96 )
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PLD( bge 4b )
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5: ands ip, r2, #28
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rsb ip, ip, #32
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addne pc, pc, ip @ C is always clear here
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b 7f
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6: nop
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ldr r3, [r1, #-4]!
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ldr r4, [r1, #-4]!
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ldr r5, [r1, #-4]!
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ldr r6, [r1, #-4]!
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ldr r7, [r1, #-4]!
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ldr r8, [r1, #-4]!
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ldr lr, [r1, #-4]!
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add pc, pc, ip
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nop
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nop
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str r3, [r0, #-4]!
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str r4, [r0, #-4]!
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str r5, [r0, #-4]!
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str r6, [r0, #-4]!
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str r7, [r0, #-4]!
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str r8, [r0, #-4]!
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str lr, [r0, #-4]!
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CALGN( bcs 2b )
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7: ldmfd sp!, {r5 - r8}
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8: movs r2, r2, lsl #31
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ldrneb r3, [r1, #-1]!
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ldrcsb r4, [r1, #-1]!
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ldrcsb ip, [r1, #-1]
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strneb r3, [r0, #-1]!
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strcsb r4, [r0, #-1]!
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strcsb ip, [r0, #-1]
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ldmfd sp!, {r0, r4, pc}
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9: cmp ip, #2
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ldrgtb r3, [r1, #-1]!
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ldrgeb r4, [r1, #-1]!
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ldrb lr, [r1, #-1]!
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strgtb r3, [r0, #-1]!
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strgeb r4, [r0, #-1]!
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subs r2, r2, ip
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strb lr, [r0, #-1]!
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blt 8b
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ands ip, r1, #3
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beq 1b
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10: bic r1, r1, #3
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cmp ip, #2
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ldr r3, [r1, #0]
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beq 17f
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blt 18f
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.macro backward_copy_shift push pull
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subs r2, r2, #28
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blt 14f
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CALGN( ands ip, r1, #31 )
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CALGN( rsb ip, ip, #32 )
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CALGN( sbcnes r4, ip, r2 ) @ C is always set here
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CALGN( subcc r2, r2, ip )
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CALGN( bcc 15f )
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11: stmfd sp!, {r5 - r9}
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PLD( pld [r1, #-4] )
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PLD( subs r2, r2, #96 )
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PLD( pld [r1, #-32] )
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PLD( blt 13f )
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PLD( pld [r1, #-64] )
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PLD( pld [r1, #-96] )
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12: PLD( pld [r1, #-128] )
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13: ldmdb r1!, {r7, r8, r9, ip}
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mov lr, r3, push #\push
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subs r2, r2, #32
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ldmdb r1!, {r3, r4, r5, r6}
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orr lr, lr, ip, pull #\pull
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mov ip, ip, push #\push
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orr ip, ip, r9, pull #\pull
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mov r9, r9, push #\push
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orr r9, r9, r8, pull #\pull
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mov r8, r8, push #\push
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orr r8, r8, r7, pull #\pull
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mov r7, r7, push #\push
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orr r7, r7, r6, pull #\pull
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mov r6, r6, push #\push
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orr r6, r6, r5, pull #\pull
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mov r5, r5, push #\push
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orr r5, r5, r4, pull #\pull
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mov r4, r4, push #\push
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orr r4, r4, r3, pull #\pull
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stmdb r0!, {r4 - r9, ip, lr}
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bge 12b
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PLD( cmn r2, #96 )
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PLD( bge 13b )
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ldmfd sp!, {r5 - r9}
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14: ands ip, r2, #28
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beq 16f
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15: mov lr, r3, push #\push
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ldr r3, [r1, #-4]!
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subs ip, ip, #4
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orr lr, lr, r3, pull #\pull
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str lr, [r0, #-4]!
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bgt 15b
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CALGN( cmp r2, #0 )
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CALGN( bge 11b )
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16: add r1, r1, #(\pull / 8)
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b 8b
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.endm
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backward_copy_shift push=8 pull=24
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17: backward_copy_shift push=16 pull=16
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18: backward_copy_shift push=24 pull=8
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