4ccf4beab8
MX23/28 use IP cores which follow a register layout I have first seen on
STMP3xxx SoCs. In this layout, every register actually has four u32:
1.) to store a value directly
2.) a SET register where every 1-bit sets the corresponding bit,
others are unaffected
3.) same with a CLR register
4.) same with a TOG (toggle) register
Also, the 2 MSBs in register 0 are always the same and can be used to reset
the IP core.
All this is strictly speaking not mach-specific (but IP core specific) and,
thus, doesn't need to be in mach-mxs/include. At least mx6 also uses IP cores
following this stmp-style. So:
Introduce a stmp-style device, put the code and defines for that in a public
place (lib/), and let drivers for stmp-style devices select that code.
To avoid regressions and ease reviewing, the actual code is simply copied from
mach-mxs. It definately wants updates, but those need a seperate patch series.
Voila, mach dependency gone, reusable code introduced. Note that I didn't
remove the duplicated code from mach-mxs yet, first the drivers have to be
converted.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
81 lines
2.1 KiB
C
81 lines
2.1 KiB
C
/*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
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* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/stmp_device.h>
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#define STMP_MODULE_CLKGATE (1 << 30)
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#define STMP_MODULE_SFTRST (1 << 31)
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/*
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* Clear the bit and poll it cleared. This is usually called with
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* a reset address and mask being either SFTRST(bit 31) or CLKGATE
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* (bit 30).
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*/
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static int stmp_clear_poll_bit(void __iomem *addr, u32 mask)
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{
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int timeout = 0x400;
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writel(mask, addr + STMP_OFFSET_REG_CLR);
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udelay(1);
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while ((readl(addr) & mask) && --timeout)
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/* nothing */;
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return !timeout;
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}
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int stmp_reset_block(void __iomem *reset_addr)
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{
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int ret;
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int timeout = 0x400;
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/* clear and poll SFTRST */
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ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
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if (unlikely(ret))
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goto error;
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/* clear CLKGATE */
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writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR);
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/* set SFTRST to reset the block */
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writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET);
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udelay(1);
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/* poll CLKGATE becoming set */
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while ((!(readl(reset_addr) & STMP_MODULE_CLKGATE)) && --timeout)
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/* nothing */;
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if (unlikely(!timeout))
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goto error;
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/* clear and poll SFTRST */
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ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
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if (unlikely(ret))
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goto error;
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/* clear and poll CLKGATE */
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ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_CLKGATE);
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if (unlikely(ret))
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goto error;
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return 0;
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error:
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pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
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return -ETIMEDOUT;
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}
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EXPORT_SYMBOL(stmp_reset_block);
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