63bd23591e
Here is a driver for the Alchemy au1550 PSC (Programmable Serial Controller) in SPI master mode. It supports dma transfers using the Alchemy descriptor based dma controller for 4-8 bits per word SPI transfers. For 9-24 bits per word transfers, pio irq based mode is used to avoid setup of dma channels from scratch on each number of bits per word change. Tested with au1550; this may also work on other MIPS Alchemy cpus, like au1200/au1210/au1250. Used extensively with SD card connected via SPI; this handles 8.1MHz SPI clock transfers using dma without any problem (the highest SPI clock freq possible with au1550 running on 324MHz). The driver supports sharing of SPI bus by multiple devices. All features of Alchemy SPI mode are supported (all SPI modes, msb/lsb first, bits per word in 4-24 range). As the SPI clock of the controller depends on main input clock that shall be configured externally, platform data structure for au1550 SPI controller driver contains mainclk_hz attribute to define the input clock rate. From this value, dividers of the controller for SPI clock are set up for required frequency. Signed-off-by: Jan Nikitenko <jan.nikitenko@gmail.com> Whitespace and section fixups. Remove partial workaround for platform setup bug in dma_mask setup; it couldn't work with multiple controllers. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
17 lines
484 B
C
17 lines
484 B
C
/*
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* au1550_spi.h - au1550 psc spi controller driver - platform data struct
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*/
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#ifndef _AU1550_SPI_H_
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#define _AU1550_SPI_H_
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struct au1550_spi_info {
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s16 bus_num; /* defines which PSC and IRQ to use */
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u32 mainclk_hz; /* main input clock frequency of PSC */
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u16 num_chipselect; /* number of chipselects supported */
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void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
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void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
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};
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#endif
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