Frieder Schrempf 598dce7068 mtd: rawnand: AMD: Also use the last page for bad block markers ... According to the datasheet of some Cypress SLC NANDs, the bad block markers can be in the first, second or last page of a block. So let's check all three locations. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>		2019-04-18 08:54:08 +02:00
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onenand	mtd: onenand: Store bad block marker position in chip struct	2019-04-18 08:54:07 +02:00
raw	mtd: rawnand: AMD: Also use the last page for bad block markers	2019-04-18 08:54:08 +02:00
spi	mtd: spinand: Implement mtd->_max_bad_blocks	2019-04-08 10:21:10 +02:00
bbt.c	mtd: nand: Fix memory allocation in nanddev_bbt_init()	2018-11-28 15:41:50 +01:00
core.c	mtd: nand: Add max_bad_eraseblocks_per_lun info to memorg	2019-04-08 10:21:08 +02:00
Kconfig	mtd: nand: Remove useless line in Kconfig	2019-04-18 08:54:01 +02:00
Makefile	mtd: nand: Add core infrastructure to support SPI NANDs	2018-07-18 09:24:10 +02:00