Peter Ujfalusi 63c3194b82 ASoC: tlv320aic3x: Mark the RESET register as volatile ... The RESET register only have one self clearing bit and it should not be cached. If it is cached, when we sync the registers back to the chip we will initiate a software reset as well, which is not desirable. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: Mark Brown <broonie@kernel.org>		2016-12-31 18:43:11 +00:00
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aoa	powerpc updates for 4.9	2016-10-07 20:19:31 -07:00
arm
atmel
core	ALSA: info: Return error for invalid read/write	2016-11-08 14:37:26 +01:00
drivers
firewire
hda
i2c
isa
mips
oss
parisc
pci	ALSA: hda - Fix mic regression by ASRock mobo fixup	2016-11-11 12:33:20 +01:00
pcmcia
ppc	powerpc updates for 4.9	2016-10-07 20:19:31 -07:00
sh
soc	ASoC: tlv320aic3x: Mark the RESET register as volatile	2016-12-31 18:43:11 +00:00
sparc	dbri: move dereference after check for NULL	2016-12-06 12:18:22 -05:00
spi
synth
usb	ALSA: usb-audio: Fix use-after-free of usb_device at disconnect	2016-11-14 22:05:04 +01:00
ac97_bus.c
Kconfig
last.c
Makefile
sound_core.c