65f1f5a2c3
This may have made sense on a paranoid day with pass 1 BCM1250 processors that were throwing cache error exception left and right for no good reason. On modern silicion that hardly makes sense and the code had gotten just an obscurity ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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arm26 | ||
cris | ||
frv | ||
h8300 | ||
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m32r | ||
m68k | ||
m68knommu | ||
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parisc | ||
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sh | ||
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xtensa |