Vineet Gupta 69cbe630f5 ARC: LLOCK/SCOND based rwlock ... With LLOCK/SCOND, the rwlock counter can be atomically updated w/o need for a guarding spin lock. This in turn elides the EXchange instruction based spinning which causes the cacheline transition to exclusive state and concurrent spinning across cores would cause the line to keep bouncing around. LLOCK/SCOND based implementation is superior as spinning on LLOCK keeps the cacheline in shared state. Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-08-04 09:26:33 +05:30
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boot	ARCv2: [axs103] bump CPU frequency from 75 to 90 MHZ	2015-07-09 17:36:31 +05:30
configs	ARCv2: [vdk] dts files and defconfig for HS38 VDK	2015-06-25 06:00:21 +05:30
include	ARC: LLOCK/SCOND based rwlock	2015-08-04 09:26:33 +05:30
kernel	ARCv2: Fix the peripheral address space detection	2015-08-03 19:34:07 +05:30
lib	ARCv2: lib: memset: Don't assume 64-bit load/stores	2015-07-20 17:44:37 +03:00
mm	ARC: Don't memzero twice in dma_alloc_coherent for __GFP_ZERO	2015-07-06 11:09:01 +05:30
oprofile
plat-axs10x	ARCv2: [axs103_smp] Reduce clk for Quad FPGA configs	2015-08-04 09:26:30 +05:30
plat-sim	ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores	2015-06-25 06:00:19 +05:30
plat-tb10x
Kbuild
Kconfig	ARCv2: allow selection of page size for MMUv4	2015-07-23 12:04:39 +03:00
Kconfig.debug	ARC: With earlycon in use, retire EARLY_PRINTK	2015-05-11 11:20:21 +05:30
Makefile	ARCv2: add knob for DIV_REV in Kconfig	2015-07-20 13:33:30 +03:00