750052dd24
Add sha1 and hmac(sha1) async hash drivers Signed-off-by: Uri Simchoni <uri@jdland.co.il> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
150 lines
3.8 KiB
C
150 lines
3.8 KiB
C
#ifndef __MV_CRYPTO_H__
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#define DIGEST_INITIAL_VAL_A 0xdd00
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#define DIGEST_INITIAL_VAL_B 0xdd04
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#define DIGEST_INITIAL_VAL_C 0xdd08
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#define DIGEST_INITIAL_VAL_D 0xdd0c
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#define DIGEST_INITIAL_VAL_E 0xdd10
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#define DES_CMD_REG 0xdd58
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#define SEC_ACCEL_CMD 0xde00
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#define SEC_CMD_EN_SEC_ACCL0 (1 << 0)
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#define SEC_CMD_EN_SEC_ACCL1 (1 << 1)
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#define SEC_CMD_DISABLE_SEC (1 << 2)
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#define SEC_ACCEL_DESC_P0 0xde04
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#define SEC_DESC_P0_PTR(x) (x)
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#define SEC_ACCEL_DESC_P1 0xde14
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#define SEC_DESC_P1_PTR(x) (x)
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#define SEC_ACCEL_CFG 0xde08
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#define SEC_CFG_STOP_DIG_ERR (1 << 0)
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#define SEC_CFG_CH0_W_IDMA (1 << 7)
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#define SEC_CFG_CH1_W_IDMA (1 << 8)
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#define SEC_CFG_ACT_CH0_IDMA (1 << 9)
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#define SEC_CFG_ACT_CH1_IDMA (1 << 10)
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#define SEC_ACCEL_STATUS 0xde0c
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#define SEC_ST_ACT_0 (1 << 0)
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#define SEC_ST_ACT_1 (1 << 1)
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/*
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* FPGA_INT_STATUS looks like a FPGA leftover and is documented only in Errata
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* 4.12. It looks like that it was part of an IRQ-controller in FPGA and
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* someone forgot to remove it while switching to the core and moving to
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* SEC_ACCEL_INT_STATUS.
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*/
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#define FPGA_INT_STATUS 0xdd68
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#define SEC_ACCEL_INT_STATUS 0xde20
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#define SEC_INT_AUTH_DONE (1 << 0)
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#define SEC_INT_DES_E_DONE (1 << 1)
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#define SEC_INT_AES_E_DONE (1 << 2)
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#define SEC_INT_AES_D_DONE (1 << 3)
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#define SEC_INT_ENC_DONE (1 << 4)
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#define SEC_INT_ACCEL0_DONE (1 << 5)
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#define SEC_INT_ACCEL1_DONE (1 << 6)
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#define SEC_INT_ACC0_IDMA_DONE (1 << 7)
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#define SEC_INT_ACC1_IDMA_DONE (1 << 8)
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#define SEC_ACCEL_INT_MASK 0xde24
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#define AES_KEY_LEN (8 * 4)
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struct sec_accel_config {
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u32 config;
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#define CFG_OP_MAC_ONLY 0
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#define CFG_OP_CRYPT_ONLY 1
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#define CFG_OP_MAC_CRYPT 2
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#define CFG_OP_CRYPT_MAC 3
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#define CFG_MACM_MD5 (4 << 4)
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#define CFG_MACM_SHA1 (5 << 4)
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#define CFG_MACM_HMAC_MD5 (6 << 4)
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#define CFG_MACM_HMAC_SHA1 (7 << 4)
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#define CFG_ENCM_DES (1 << 8)
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#define CFG_ENCM_3DES (2 << 8)
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#define CFG_ENCM_AES (3 << 8)
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#define CFG_DIR_ENC (0 << 12)
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#define CFG_DIR_DEC (1 << 12)
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#define CFG_ENC_MODE_ECB (0 << 16)
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#define CFG_ENC_MODE_CBC (1 << 16)
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#define CFG_3DES_EEE (0 << 20)
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#define CFG_3DES_EDE (1 << 20)
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#define CFG_AES_LEN_128 (0 << 24)
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#define CFG_AES_LEN_192 (1 << 24)
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#define CFG_AES_LEN_256 (2 << 24)
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#define CFG_NOT_FRAG (0 << 30)
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#define CFG_FIRST_FRAG (1 << 30)
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#define CFG_LAST_FRAG (2 << 30)
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#define CFG_MID_FRAG (3 << 30)
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u32 enc_p;
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#define ENC_P_SRC(x) (x)
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#define ENC_P_DST(x) ((x) << 16)
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u32 enc_len;
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#define ENC_LEN(x) (x)
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u32 enc_key_p;
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#define ENC_KEY_P(x) (x)
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u32 enc_iv;
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#define ENC_IV_POINT(x) ((x) << 0)
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#define ENC_IV_BUF_POINT(x) ((x) << 16)
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u32 mac_src_p;
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#define MAC_SRC_DATA_P(x) (x)
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#define MAC_SRC_TOTAL_LEN(x) ((x) << 16)
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u32 mac_digest;
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#define MAC_DIGEST_P(x) (x)
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#define MAC_FRAG_LEN(x) ((x) << 16)
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u32 mac_iv;
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#define MAC_INNER_IV_P(x) (x)
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#define MAC_OUTER_IV_P(x) ((x) << 16)
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}__attribute__ ((packed));
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/*
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* /-----------\ 0
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* | ACCEL CFG | 4 * 8
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* |-----------| 0x20
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* | CRYPT KEY | 8 * 4
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* |-----------| 0x40
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* | IV IN | 4 * 4
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* |-----------| 0x40 (inplace)
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* | IV BUF | 4 * 4
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* |-----------| 0x80
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* | DATA IN | 16 * x (max ->max_req_size)
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* |-----------| 0x80 (inplace operation)
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* | DATA OUT | 16 * x (max ->max_req_size)
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* \-----------/ SRAM size
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*/
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/* Hashing memory map:
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* /-----------\ 0
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* | ACCEL CFG | 4 * 8
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* |-----------| 0x20
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* | Inner IV | 5 * 4
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* |-----------| 0x34
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* | Outer IV | 5 * 4
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* |-----------| 0x48
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* | Output BUF| 5 * 4
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* |-----------| 0x80
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* | DATA IN | 64 * x (max ->max_req_size)
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* \-----------/ SRAM size
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*/
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#define SRAM_CONFIG 0x00
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#define SRAM_DATA_KEY_P 0x20
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#define SRAM_DATA_IV 0x40
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#define SRAM_DATA_IV_BUF 0x40
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#define SRAM_DATA_IN_START 0x80
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#define SRAM_DATA_OUT_START 0x80
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#define SRAM_HMAC_IV_IN 0x20
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#define SRAM_HMAC_IV_OUT 0x34
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#define SRAM_DIGEST_BUF 0x48
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#define SRAM_CFG_SPACE 0x80
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#endif
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