6f7e0d9d08
Combine sensor group-related data structures into struct tegra_tsensor_group. This provides a single location for sensor group data storage. More sensor group data will be added in subsequent patches. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
555 lines
15 KiB
C
555 lines
15 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Mikko Perttunen <mperttunen@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/thermal.h>
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#include <soc/tegra/fuse.h>
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#include <dt-bindings/thermal/tegra124-soctherm.h>
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#define SENSOR_CONFIG0 0
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#define SENSOR_CONFIG0_STOP BIT(0)
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#define SENSOR_CONFIG0_TALL_SHIFT 8
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#define SENSOR_CONFIG0_TCALC_OVER BIT(4)
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#define SENSOR_CONFIG0_OVER BIT(3)
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#define SENSOR_CONFIG0_CPTR_OVER BIT(2)
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#define SENSOR_CONFIG1 4
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#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
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#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
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#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
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#define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
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#define SENSOR_CONFIG2 8
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#define SENSOR_CONFIG2_THERMA_SHIFT 16
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#define SENSOR_CONFIG2_THERMB_SHIFT 0
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#define SENSOR_PDIV 0x1c0
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#define SENSOR_PDIV_T124 0x8888
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#define SENSOR_PDIV_CPU_MASK (0xf << 12)
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#define SENSOR_PDIV_GPU_MASK (0xf << 8)
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#define SENSOR_PDIV_MEM_MASK (0xf << 4)
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#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
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#define SENSOR_HOTSPOT_OFF 0x1c4
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#define SENSOR_HOTSPOT_OFF_T124 0x00060600
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#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
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#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
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#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
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#define SENSOR_TEMP1 0x1c8
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#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16)
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#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
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#define SENSOR_TEMP2 0x1cc
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#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
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#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
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#define READBACK_VALUE_MASK 0xff00
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#define READBACK_VALUE_SHIFT 8
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#define READBACK_ADD_HALF BIT(7)
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#define READBACK_NEGATE BIT(0)
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#define FUSE_TSENSOR8_CALIB 0x180
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#define FUSE_SPARE_REALIGNMENT_REG_0 0x1fc
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#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
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#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
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#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
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#define FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK 0x3ff
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#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK (0x7ff << 10)
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#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT 10
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#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_MASK 0x3f
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#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK (0x1f << 21)
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#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT 21
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#define NOMINAL_CALIB_FT_T124 105
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#define NOMINAL_CALIB_CP_T124 25
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/* get val from register(r) mask bits(m) */
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#define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
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/* set val(v) to mask bits(m) of register(r) */
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#define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
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(((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
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/**
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* struct tegra_tsensor_group - SOC_THERM sensor group data
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* @name: short name of the temperature sensor group
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* @id: numeric ID of the temperature sensor group
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* @sensor_temp_offset: offset of the SENSOR_TEMP* register
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* @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
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* @pdiv: the sensor count post-divider to use during runtime
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* @pdiv_ate: the sensor count post-divider used during automated test
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* @pdiv_mask: register bitfield mask for the PDIV field for this sensor
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* @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
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PLLX sensor group
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* @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
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*/
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struct tegra_tsensor_group {
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const char *name;
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u8 id;
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u16 sensor_temp_offset;
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u32 sensor_temp_mask;
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u32 pdiv, pdiv_ate, pdiv_mask;
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u32 pllx_hotspot_diff, pllx_hotspot_mask;
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};
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struct tegra_tsensor_configuration {
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u32 tall, tiddq_en, ten_count, tsample, tsample_ate;
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};
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struct tegra_tsensor {
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const struct tegra_tsensor_configuration *config;
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u32 base, calib_fuse_offset;
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/* Correction values used to modify values read from calibration fuses */
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s32 fuse_corr_alpha, fuse_corr_beta;
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const struct tegra_tsensor_group *group;
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};
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struct tegra_thermctl_zone {
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void __iomem *reg;
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u32 mask;
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};
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static const struct tegra_tsensor_configuration t124_tsensor_config = {
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.tall = 16300,
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.tiddq_en = 1,
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.ten_count = 1,
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.tsample = 120,
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.tsample_ate = 480,
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};
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static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
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.id = TEGRA124_SOCTHERM_SENSOR_CPU,
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.name = "cpu",
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.sensor_temp_offset = SENSOR_TEMP1,
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.sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_CPU_MASK,
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.pllx_hotspot_diff = 10,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
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};
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static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
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.id = TEGRA124_SOCTHERM_SENSOR_GPU,
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.name = "gpu",
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.sensor_temp_offset = SENSOR_TEMP1,
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.sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_GPU_MASK,
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.pllx_hotspot_diff = 5,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
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};
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static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
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.id = TEGRA124_SOCTHERM_SENSOR_PLLX,
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.name = "pll",
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.sensor_temp_offset = SENSOR_TEMP2,
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.sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_PLLX_MASK,
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.pllx_hotspot_diff = 0,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
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};
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static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
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.id = TEGRA124_SOCTHERM_SENSOR_MEM,
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.name = "mem",
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.sensor_temp_offset = SENSOR_TEMP2,
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.sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_MEM_MASK,
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};
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static const struct tegra_tsensor_group *
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tegra124_tsensor_groups[TEGRA124_SOCTHERM_SENSOR_NUM] = {
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&tegra124_tsensor_group_cpu,
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&tegra124_tsensor_group_gpu,
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&tegra124_tsensor_group_pll,
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&tegra124_tsensor_group_mem,
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};
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static const struct tegra_tsensor t124_tsensors[] = {
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{
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.config = &t124_tsensor_config,
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.base = 0xc0,
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.calib_fuse_offset = 0x098,
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.fuse_corr_alpha = 1135400,
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.fuse_corr_beta = -6266900,
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.group = &tegra124_tsensor_group_cpu,
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},
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{
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.config = &t124_tsensor_config,
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.base = 0xe0,
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.calib_fuse_offset = 0x084,
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.fuse_corr_alpha = 1122220,
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.fuse_corr_beta = -5700700,
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.group = &tegra124_tsensor_group_cpu,
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},
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{
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.config = &t124_tsensor_config,
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.base = 0x100,
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.calib_fuse_offset = 0x088,
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.fuse_corr_alpha = 1127000,
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.fuse_corr_beta = -6768200,
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.group = &tegra124_tsensor_group_cpu,
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},
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{
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.config = &t124_tsensor_config,
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.base = 0x120,
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.calib_fuse_offset = 0x12c,
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.fuse_corr_alpha = 1110900,
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.fuse_corr_beta = -6232000,
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.group = &tegra124_tsensor_group_cpu,
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},
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{
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.config = &t124_tsensor_config,
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.base = 0x140,
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.calib_fuse_offset = 0x158,
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.fuse_corr_alpha = 1122300,
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.fuse_corr_beta = -5936400,
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.group = &tegra124_tsensor_group_mem,
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},
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{
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.config = &t124_tsensor_config,
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.base = 0x160,
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.calib_fuse_offset = 0x15c,
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.fuse_corr_alpha = 1145700,
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.fuse_corr_beta = -7124600,
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.group = &tegra124_tsensor_group_mem,
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},
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{
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.config = &t124_tsensor_config,
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.base = 0x180,
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.calib_fuse_offset = 0x154,
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.fuse_corr_alpha = 1120100,
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.fuse_corr_beta = -6000500,
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.group = &tegra124_tsensor_group_gpu,
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},
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{
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.config = &t124_tsensor_config,
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.base = 0x1a0,
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.calib_fuse_offset = 0x160,
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.fuse_corr_alpha = 1106500,
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.fuse_corr_beta = -6729300,
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.group = &tegra124_tsensor_group_pll,
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},
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};
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struct tegra_soctherm {
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struct reset_control *reset;
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struct clk *clock_tsensor;
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struct clk *clock_soctherm;
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void __iomem *regs;
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};
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struct tsensor_shared_calibration {
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u32 base_cp, base_ft;
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u32 actual_temp_cp, actual_temp_ft;
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};
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static int calculate_shared_calibration(struct tsensor_shared_calibration *r)
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{
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u32 val, shifted_cp, shifted_ft;
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int err;
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err = tegra_fuse_readl(FUSE_TSENSOR8_CALIB, &val);
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if (err)
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return err;
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r->base_cp = val & FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK;
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r->base_ft = (val & FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK)
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>> FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT;
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val = ((val & FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK)
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>> FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT);
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shifted_ft = sign_extend32(val, 4);
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err = tegra_fuse_readl(FUSE_SPARE_REALIGNMENT_REG_0, &val);
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if (err)
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return err;
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shifted_cp = sign_extend32(val, 5);
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r->actual_temp_cp = 2 * NOMINAL_CALIB_CP_T124 + shifted_cp;
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r->actual_temp_ft = 2 * NOMINAL_CALIB_FT_T124 + shifted_ft;
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return 0;
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}
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static s64 div64_s64_precise(s64 a, s64 b)
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{
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s64 r, al;
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/* Scale up for increased precision division */
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al = a << 16;
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r = div64_s64(al * 2 + 1, 2 * b);
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return r >> 16;
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}
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static int
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calculate_tsensor_calibration(const struct tegra_tsensor *sensor,
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const struct tsensor_shared_calibration *shared,
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u32 *calib)
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{
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u32 val;
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s32 actual_tsensor_ft, actual_tsensor_cp, delta_sens, delta_temp,
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mult, div;
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s16 therma, thermb;
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s64 tmp;
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int err;
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err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
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if (err)
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return err;
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actual_tsensor_cp = (shared->base_cp * 64) + sign_extend32(val, 12);
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val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK)
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>> FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
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actual_tsensor_ft = (shared->base_ft * 32) + sign_extend32(val, 12);
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delta_sens = actual_tsensor_ft - actual_tsensor_cp;
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delta_temp = shared->actual_temp_ft - shared->actual_temp_cp;
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mult = sensor->group->pdiv * sensor->config->tsample_ate;
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div = sensor->config->tsample * sensor->group->pdiv_ate;
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therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
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(s64) delta_sens * div);
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tmp = (s64)actual_tsensor_ft * shared->actual_temp_cp -
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(s64)actual_tsensor_cp * shared->actual_temp_ft;
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thermb = div64_s64_precise(tmp, (s64)delta_sens);
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therma = div64_s64_precise((s64)therma * sensor->fuse_corr_alpha,
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(s64)1000000LL);
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thermb = div64_s64_precise((s64)thermb * sensor->fuse_corr_alpha +
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sensor->fuse_corr_beta, (s64)1000000LL);
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*calib = ((u16)therma << SENSOR_CONFIG2_THERMA_SHIFT) |
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((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
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return 0;
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}
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static int enable_tsensor(struct tegra_soctherm *tegra,
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const struct tegra_tsensor *sensor,
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const struct tsensor_shared_calibration *shared)
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{
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void __iomem *base = tegra->regs + sensor->base;
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unsigned int val;
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u32 calib;
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int err;
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err = calculate_tsensor_calibration(sensor, shared, &calib);
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if (err)
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return err;
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val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
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writel(val, base + SENSOR_CONFIG0);
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val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
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val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
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val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
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val |= SENSOR_CONFIG1_TEMP_ENABLE;
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writel(val, base + SENSOR_CONFIG1);
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writel(calib, base + SENSOR_CONFIG2);
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return 0;
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}
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/*
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* Translate from soctherm readback format to millicelsius.
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* The soctherm readback format in bits is as follows:
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* TTTTTTTT H______N
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* where T's contain the temperature in Celsius,
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* H denotes an addition of 0.5 Celsius and N denotes negation
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* of the final value.
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*/
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static int translate_temp(u16 val)
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{
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long t;
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t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
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if (val & READBACK_ADD_HALF)
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t += 500;
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if (val & READBACK_NEGATE)
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t *= -1;
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return t;
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}
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static int tegra_thermctl_get_temp(void *data, int *out_temp)
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{
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struct tegra_thermctl_zone *zone = data;
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u32 val;
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val = readl(zone->reg);
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val = REG_GET_MASK(val, zone->mask);
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*out_temp = translate_temp(val);
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return 0;
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}
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static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
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.get_temp = tegra_thermctl_get_temp,
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};
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static const struct of_device_id tegra_soctherm_of_match[] = {
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{ .compatible = "nvidia,tegra124-soctherm" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
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static int tegra_soctherm_probe(struct platform_device *pdev)
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{
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struct tegra_soctherm *tegra;
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struct thermal_zone_device *z;
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struct tsensor_shared_calibration shared_calib;
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struct resource *res;
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unsigned int i;
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int err;
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const struct tegra_tsensor *tsensors = t124_tsensors;
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const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
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tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
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if (!tegra)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tegra->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(tegra->regs))
|
|
return PTR_ERR(tegra->regs);
|
|
|
|
tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
|
|
if (IS_ERR(tegra->reset)) {
|
|
dev_err(&pdev->dev, "can't get soctherm reset\n");
|
|
return PTR_ERR(tegra->reset);
|
|
}
|
|
|
|
tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
|
|
if (IS_ERR(tegra->clock_tsensor)) {
|
|
dev_err(&pdev->dev, "can't get tsensor clock\n");
|
|
return PTR_ERR(tegra->clock_tsensor);
|
|
}
|
|
|
|
tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
|
|
if (IS_ERR(tegra->clock_soctherm)) {
|
|
dev_err(&pdev->dev, "can't get soctherm clock\n");
|
|
return PTR_ERR(tegra->clock_soctherm);
|
|
}
|
|
|
|
reset_control_assert(tegra->reset);
|
|
|
|
err = clk_prepare_enable(tegra->clock_soctherm);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_prepare_enable(tegra->clock_tsensor);
|
|
if (err) {
|
|
clk_disable_unprepare(tegra->clock_soctherm);
|
|
return err;
|
|
}
|
|
|
|
reset_control_deassert(tegra->reset);
|
|
|
|
/* Initialize raw sensors */
|
|
|
|
err = calculate_shared_calibration(&shared_calib);
|
|
if (err)
|
|
goto disable_clocks;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(t124_tsensors); ++i) {
|
|
err = enable_tsensor(tegra, tsensors + i, &shared_calib);
|
|
if (err)
|
|
goto disable_clocks;
|
|
}
|
|
|
|
writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
|
|
writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
|
|
|
|
/* Initialize thermctl sensors */
|
|
|
|
for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
|
|
struct tegra_thermctl_zone *zone =
|
|
devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
|
|
if (!zone) {
|
|
err = -ENOMEM;
|
|
goto disable_clocks;
|
|
}
|
|
|
|
zone->reg = tegra->regs + ttgs[i]->sensor_temp_offset;
|
|
zone->mask = ttgs[i]->sensor_temp_mask;
|
|
|
|
z = devm_thermal_zone_of_sensor_register(&pdev->dev,
|
|
ttgs[i]->id, zone,
|
|
&tegra_of_thermal_ops);
|
|
if (IS_ERR(z)) {
|
|
err = PTR_ERR(z);
|
|
dev_err(&pdev->dev, "failed to register sensor: %d\n",
|
|
err);
|
|
goto disable_clocks;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
disable_clocks:
|
|
clk_disable_unprepare(tegra->clock_tsensor);
|
|
clk_disable_unprepare(tegra->clock_soctherm);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int tegra_soctherm_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
|
|
|
|
clk_disable_unprepare(tegra->clock_tsensor);
|
|
clk_disable_unprepare(tegra->clock_soctherm);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver tegra_soctherm_driver = {
|
|
.probe = tegra_soctherm_probe,
|
|
.remove = tegra_soctherm_remove,
|
|
.driver = {
|
|
.name = "tegra-soctherm",
|
|
.of_match_table = tegra_soctherm_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(tegra_soctherm_driver);
|
|
|
|
MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
|
|
MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
|
|
MODULE_LICENSE("GPL v2");
|