529 lines
15 KiB
C
529 lines
15 KiB
C
/* Copyright (C) 1999,2001
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*
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* Author: J.E.J.Bottomley@HansenPartnership.com
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*
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* Standard include definitions for the NCR Voyager system */
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#undef VOYAGER_DEBUG
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#undef VOYAGER_CAT_DEBUG
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#ifdef VOYAGER_DEBUG
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#define VDEBUG(x) printk x
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#else
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#define VDEBUG(x)
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#endif
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/* There are three levels of voyager machine: 3,4 and 5. The rule is
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* if it's less than 3435 it's a Level 3 except for a 3360 which is
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* a level 4. A 3435 or above is a Level 5 */
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#define VOYAGER_LEVEL5_AND_ABOVE 0x3435
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#define VOYAGER_LEVEL4 0x3360
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/* The L4 DINO ASIC */
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#define VOYAGER_DINO 0x43
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/* voyager ports in standard I/O space */
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#define VOYAGER_MC_SETUP 0x96
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#define VOYAGER_CAT_CONFIG_PORT 0x97
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# define VOYAGER_CAT_DESELECT 0xff
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#define VOYAGER_SSPB_RELOCATION_PORT 0x98
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/* Valid CAT controller commands */
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/* start instruction register cycle */
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#define VOYAGER_CAT_IRCYC 0x01
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/* start data register cycle */
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#define VOYAGER_CAT_DRCYC 0x02
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/* move to execute state */
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#define VOYAGER_CAT_RUN 0x0F
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/* end operation */
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#define VOYAGER_CAT_END 0x80
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/* hold in idle state */
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#define VOYAGER_CAT_HOLD 0x90
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/* single step an "intest" vector */
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#define VOYAGER_CAT_STEP 0xE0
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/* return cat controller to CLEMSON mode */
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#define VOYAGER_CAT_CLEMSON 0xFF
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/* the default cat command header */
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#define VOYAGER_CAT_HEADER 0x7F
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/* the range of possible CAT module ids in the system */
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#define VOYAGER_MIN_MODULE 0x10
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#define VOYAGER_MAX_MODULE 0x1f
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/* The voyager registers per asic */
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#define VOYAGER_ASIC_ID_REG 0x00
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#define VOYAGER_ASIC_TYPE_REG 0x01
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/* the sub address registers can be made auto incrementing on reads */
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#define VOYAGER_AUTO_INC_REG 0x02
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# define VOYAGER_AUTO_INC 0x04
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# define VOYAGER_NO_AUTO_INC 0xfb
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#define VOYAGER_SUBADDRDATA 0x03
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#define VOYAGER_SCANPATH 0x05
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# define VOYAGER_CONNECT_ASIC 0x01
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# define VOYAGER_DISCONNECT_ASIC 0xfe
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#define VOYAGER_SUBADDRLO 0x06
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#define VOYAGER_SUBADDRHI 0x07
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#define VOYAGER_SUBMODSELECT 0x08
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#define VOYAGER_SUBMODPRESENT 0x09
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#define VOYAGER_SUBADDR_LO 0xff
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#define VOYAGER_SUBADDR_HI 0xffff
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/* the maximum size of a scan path -- used to form instructions */
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#define VOYAGER_MAX_SCAN_PATH 0x100
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/* the biggest possible register size (in bytes) */
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#define VOYAGER_MAX_REG_SIZE 4
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/* Total number of possible modules (including submodules) */
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#define VOYAGER_MAX_MODULES 16
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/* Largest number of asics per module */
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#define VOYAGER_MAX_ASICS_PER_MODULE 7
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/* the CAT asic of each module is always the first one */
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#define VOYAGER_CAT_ID 0
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#define VOYAGER_PSI 0x1a
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/* voyager instruction operations and registers */
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#define VOYAGER_READ_CONFIG 0x1
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#define VOYAGER_WRITE_CONFIG 0x2
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#define VOYAGER_BYPASS 0xff
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typedef struct voyager_asic {
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__u8 asic_addr; /* ASIC address; Level 4 */
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__u8 asic_type; /* ASIC type */
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__u8 asic_id; /* ASIC id */
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__u8 jtag_id[4]; /* JTAG id */
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__u8 asic_location; /* Location within scan path; start w/ 0 */
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__u8 bit_location; /* Location within bit stream; start w/ 0 */
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__u8 ireg_length; /* Instruction register length */
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__u16 subaddr; /* Amount of sub address space */
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struct voyager_asic *next; /* Next asic in linked list */
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} voyager_asic_t;
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typedef struct voyager_module {
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__u8 module_addr; /* Module address */
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__u8 scan_path_connected; /* Scan path connected */
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__u16 ee_size; /* Size of the EEPROM */
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__u16 num_asics; /* Number of Asics */
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__u16 inst_bits; /* Instruction bits in the scan path */
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__u16 largest_reg; /* Largest register in the scan path */
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__u16 smallest_reg; /* Smallest register in the scan path */
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voyager_asic_t *asic; /* First ASIC in scan path (CAT_I) */
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struct voyager_module *submodule; /* Submodule pointer */
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struct voyager_module *next; /* Next module in linked list */
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} voyager_module_t;
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typedef struct voyager_eeprom_hdr {
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__u8 module_id[4];
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__u8 version_id;
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__u8 config_id;
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__u16 boundry_id; /* boundary scan id */
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__u16 ee_size; /* size of EEPROM */
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__u8 assembly[11]; /* assembly # */
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__u8 assembly_rev; /* assembly rev */
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__u8 tracer[4]; /* tracer number */
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__u16 assembly_cksum; /* asm checksum */
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__u16 power_consump; /* pwr requirements */
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__u16 num_asics; /* number of asics */
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__u16 bist_time; /* min. bist time */
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__u16 err_log_offset; /* error log offset */
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__u16 scan_path_offset;/* scan path offset */
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__u16 cct_offset;
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__u16 log_length; /* length of err log */
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__u16 xsum_end; /* offset to end of
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checksum */
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__u8 reserved[4];
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__u8 sflag; /* starting sentinal */
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__u8 part_number[13]; /* prom part number */
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__u8 version[10]; /* version number */
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__u8 signature[8];
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__u16 eeprom_chksum;
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__u32 data_stamp_offset;
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__u8 eflag ; /* ending sentinal */
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} __attribute__((packed)) voyager_eprom_hdr_t;
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#define VOYAGER_EPROM_SIZE_OFFSET \
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((__u16)(&(((voyager_eprom_hdr_t *)0)->ee_size)))
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#define VOYAGER_XSUM_END_OFFSET 0x2a
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/* the following three definitions are for internal table layouts
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* in the module EPROMs. We really only care about the IDs and
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* offsets */
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typedef struct voyager_sp_table {
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__u8 asic_id;
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__u8 bypass_flag;
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__u16 asic_data_offset;
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__u16 config_data_offset;
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} __attribute__((packed)) voyager_sp_table_t;
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typedef struct voyager_jtag_table {
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__u8 icode[4];
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__u8 runbist[4];
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__u8 intest[4];
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__u8 samp_preld[4];
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__u8 ireg_len;
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} __attribute__((packed)) voyager_jtt_t;
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typedef struct voyager_asic_data_table {
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__u8 jtag_id[4];
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__u16 length_bsr;
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__u16 length_bist_reg;
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__u32 bist_clk;
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__u16 subaddr_bits;
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__u16 seed_bits;
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__u16 sig_bits;
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__u16 jtag_offset;
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} __attribute__((packed)) voyager_at_t;
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/* Voyager Interrupt Controller (VIC) registers */
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/* Base to add to Cross Processor Interrupts (CPIs) when triggering
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* the CPU IRQ line */
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/* register defines for the WCBICs (one per processor) */
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#define VOYAGER_WCBIC0 0x41 /* bus A node P1 processor 0 */
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#define VOYAGER_WCBIC1 0x49 /* bus A node P1 processor 1 */
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#define VOYAGER_WCBIC2 0x51 /* bus A node P2 processor 0 */
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#define VOYAGER_WCBIC3 0x59 /* bus A node P2 processor 1 */
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#define VOYAGER_WCBIC4 0x61 /* bus B node P1 processor 0 */
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#define VOYAGER_WCBIC5 0x69 /* bus B node P1 processor 1 */
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#define VOYAGER_WCBIC6 0x71 /* bus B node P2 processor 0 */
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#define VOYAGER_WCBIC7 0x79 /* bus B node P2 processor 1 */
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/* top of memory registers */
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#define VOYAGER_WCBIC_TOM_L 0x4
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#define VOYAGER_WCBIC_TOM_H 0x5
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/* register defines for Voyager Memory Contol (VMC)
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* these are present on L4 machines only */
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#define VOYAGER_VMC1 0x81
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#define VOYAGER_VMC2 0x91
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#define VOYAGER_VMC3 0xa1
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#define VOYAGER_VMC4 0xb1
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/* VMC Ports */
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#define VOYAGER_VMC_MEMORY_SETUP 0x9
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# define VMC_Interleaving 0x01
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# define VMC_4Way 0x02
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# define VMC_EvenCacheLines 0x04
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# define VMC_HighLine 0x08
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# define VMC_Start0_Enable 0x20
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# define VMC_Start1_Enable 0x40
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# define VMC_Vremap 0x80
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#define VOYAGER_VMC_BANK_DENSITY 0xa
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# define VMC_BANK_EMPTY 0
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# define VMC_BANK_4MB 1
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# define VMC_BANK_16MB 2
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# define VMC_BANK_64MB 3
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# define VMC_BANK0_MASK 0x03
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# define VMC_BANK1_MASK 0x0C
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# define VMC_BANK2_MASK 0x30
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# define VMC_BANK3_MASK 0xC0
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/* Magellan Memory Controller (MMC) defines - present on L5 */
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#define VOYAGER_MMC_ASIC_ID 1
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/* the two memory modules corresponding to memory cards in the system */
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#define VOYAGER_MMC_MEMORY0_MODULE 0x14
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#define VOYAGER_MMC_MEMORY1_MODULE 0x15
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/* the Magellan Memory Address (MMA) defines */
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#define VOYAGER_MMA_ASIC_ID 2
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/* Submodule number for the Quad Baseboard */
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#define VOYAGER_QUAD_BASEBOARD 1
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/* ASIC defines for the Quad Baseboard */
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#define VOYAGER_QUAD_QDATA0 1
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#define VOYAGER_QUAD_QDATA1 2
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#define VOYAGER_QUAD_QABC 3
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/* Useful areas in extended CMOS */
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#define VOYAGER_PROCESSOR_PRESENT_MASK 0x88a
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#define VOYAGER_MEMORY_CLICKMAP 0xa23
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#define VOYAGER_DUMP_LOCATION 0xb1a
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/* SUS In Control bit - used to tell SUS that we don't need to be
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* babysat anymore */
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#define VOYAGER_SUS_IN_CONTROL_PORT 0x3ff
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# define VOYAGER_IN_CONTROL_FLAG 0x80
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/* Voyager PSI defines */
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#define VOYAGER_PSI_STATUS_REG 0x08
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# define PSI_DC_FAIL 0x01
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# define PSI_MON 0x02
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# define PSI_FAULT 0x04
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# define PSI_ALARM 0x08
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# define PSI_CURRENT 0x10
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# define PSI_DVM 0x20
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# define PSI_PSCFAULT 0x40
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# define PSI_STAT_CHG 0x80
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#define VOYAGER_PSI_SUPPLY_REG 0x8000
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/* read */
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# define PSI_FAIL_DC 0x01
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# define PSI_FAIL_AC 0x02
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# define PSI_MON_INT 0x04
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# define PSI_SWITCH_OFF 0x08
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# define PSI_HX_OFF 0x10
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# define PSI_SECURITY 0x20
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# define PSI_CMOS_BATT_LOW 0x40
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# define PSI_CMOS_BATT_FAIL 0x80
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/* write */
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# define PSI_CLR_SWITCH_OFF 0x13
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# define PSI_CLR_HX_OFF 0x14
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# define PSI_CLR_CMOS_BATT_FAIL 0x17
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#define VOYAGER_PSI_MASK 0x8001
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# define PSI_MASK_MASK 0x10
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#define VOYAGER_PSI_AC_FAIL_REG 0x8004
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#define AC_FAIL_STAT_CHANGE 0x80
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#define VOYAGER_PSI_GENERAL_REG 0x8007
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/* read */
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# define PSI_SWITCH_ON 0x01
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# define PSI_SWITCH_ENABLED 0x02
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# define PSI_ALARM_ENABLED 0x08
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# define PSI_SECURE_ENABLED 0x10
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# define PSI_COLD_RESET 0x20
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# define PSI_COLD_START 0x80
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/* write */
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# define PSI_POWER_DOWN 0x10
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# define PSI_SWITCH_DISABLE 0x01
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# define PSI_SWITCH_ENABLE 0x11
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# define PSI_CLEAR 0x12
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# define PSI_ALARM_DISABLE 0x03
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# define PSI_ALARM_ENABLE 0x13
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# define PSI_CLEAR_COLD_RESET 0x05
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# define PSI_SET_COLD_RESET 0x15
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# define PSI_CLEAR_COLD_START 0x07
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# define PSI_SET_COLD_START 0x17
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struct voyager_bios_info {
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__u8 len;
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__u8 major;
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__u8 minor;
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__u8 debug;
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__u8 num_classes;
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__u8 class_1;
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__u8 class_2;
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};
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/* The following structures and definitions are for the Kernel/SUS
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* interface these are needed to find out how SUS initialised any Quad
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* boards in the system */
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#define NUMBER_OF_MC_BUSSES 2
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#define SLOTS_PER_MC_BUS 8
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#define MAX_CPUS 16 /* 16 way CPU system */
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#define MAX_PROCESSOR_BOARDS 4 /* 4 processor slot system */
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#define MAX_CACHE_LEVELS 4 /* # of cache levels supported */
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#define MAX_SHARED_CPUS 4 /* # of CPUs that can share a LARC */
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#define NUMBER_OF_POS_REGS 8
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typedef struct {
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__u8 MC_Slot;
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__u8 POS_Values[NUMBER_OF_POS_REGS];
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} __attribute__((packed)) MC_SlotInformation_t;
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struct QuadDescription {
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__u8 Type; /* for type 0 (DYADIC or MONADIC) all fields
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* will be zero except for slot */
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__u8 StructureVersion;
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__u32 CPI_BaseAddress;
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__u32 LARC_BankSize;
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__u32 LocalMemoryStateBits;
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__u8 Slot; /* Processor slots 1 - 4 */
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} __attribute__((packed));
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struct ProcBoardInfo {
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__u8 Type;
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__u8 StructureVersion;
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__u8 NumberOfBoards;
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struct QuadDescription QuadData[MAX_PROCESSOR_BOARDS];
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} __attribute__((packed));
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struct CacheDescription {
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__u8 Level;
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__u32 TotalSize;
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__u16 LineSize;
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__u8 Associativity;
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__u8 CacheType;
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__u8 WriteType;
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__u8 Number_CPUs_SharedBy;
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__u8 Shared_CPUs_Hardware_IDs[MAX_SHARED_CPUS];
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} __attribute__((packed));
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struct CPU_Description {
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__u8 CPU_HardwareId;
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char *FRU_String;
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__u8 NumberOfCacheLevels;
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struct CacheDescription CacheLevelData[MAX_CACHE_LEVELS];
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} __attribute__((packed));
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struct CPU_Info {
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__u8 Type;
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__u8 StructureVersion;
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__u8 NumberOf_CPUs;
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struct CPU_Description CPU_Data[MAX_CPUS];
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} __attribute__((packed));
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/*
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* This structure will be used by SUS and the OS.
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* The assumption about this structure is that no blank space is
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* packed in it by our friend the compiler.
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*/
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typedef struct {
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__u8 Mailbox_SUS; /* Written to by SUS to give
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commands/response to the OS */
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__u8 Mailbox_OS; /* Written to by the OS to give
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commands/response to SUS */
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__u8 SUS_MailboxVersion; /* Tells the OS which iteration of the
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interface SUS supports */
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__u8 OS_MailboxVersion; /* Tells SUS which iteration of the
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interface the OS supports */
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__u32 OS_Flags; /* Flags set by the OS as info for
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SUS */
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__u32 SUS_Flags; /* Flags set by SUS as info
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for the OS */
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__u32 WatchDogPeriod; /* Watchdog period (in seconds) which
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the DP uses to see if the OS
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is dead */
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__u32 WatchDogCount; /* Updated by the OS on every tic. */
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__u32 MemoryFor_SUS_ErrorLog; /* Flat 32 bit address which tells SUS
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where to stuff the SUS error log
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on a dump */
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MC_SlotInformation_t MC_SlotInfo[NUMBER_OF_MC_BUSSES*SLOTS_PER_MC_BUS];
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/* Storage for MCA POS data */
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/* All new SECOND_PASS_INTERFACE fields added from this point */
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struct ProcBoardInfo *BoardData;
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struct CPU_Info *CPU_Data;
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/* All new fields must be added from this point */
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} Voyager_KernelSUS_Mbox_t;
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/* structure for finding the right memory address to send a QIC CPI to */
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struct voyager_qic_cpi {
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/* Each cache line (32 bytes) can trigger a cpi. The cpi
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* read/write may occur anywhere in the cache line---pick the
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* middle to be safe */
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struct {
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__u32 pad1[3];
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__u32 cpi;
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__u32 pad2[4];
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} qic_cpi[8];
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};
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struct voyager_status {
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__u32 power_fail:1;
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__u32 switch_off:1;
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__u32 request_from_kernel:1;
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};
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struct voyager_psi_regs {
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__u8 cat_id;
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__u8 cat_dev;
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__u8 cat_control;
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__u8 subaddr;
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__u8 dummy4;
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__u8 checkbit;
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__u8 subaddr_low;
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__u8 subaddr_high;
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__u8 intstatus;
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__u8 stat1;
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__u8 stat3;
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__u8 fault;
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__u8 tms;
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__u8 gen;
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__u8 sysconf;
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__u8 dummy15;
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};
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struct voyager_psi_subregs {
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__u8 supply;
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__u8 mask;
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__u8 present;
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__u8 DCfail;
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__u8 ACfail;
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__u8 fail;
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__u8 UPSfail;
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__u8 genstatus;
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};
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struct voyager_psi {
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struct voyager_psi_regs regs;
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struct voyager_psi_subregs subregs;
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};
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struct voyager_SUS {
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#define VOYAGER_DUMP_BUTTON_NMI 0x1
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#define VOYAGER_SUS_VALID 0x2
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#define VOYAGER_SYSINT_COMPLETE 0x3
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__u8 SUS_mbox;
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#define VOYAGER_NO_COMMAND 0x0
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#define VOYAGER_IGNORE_DUMP 0x1
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#define VOYAGER_DO_DUMP 0x2
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#define VOYAGER_SYSINT_HANDSHAKE 0x3
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#define VOYAGER_DO_MEM_DUMP 0x4
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#define VOYAGER_SYSINT_WAS_RECOVERED 0x5
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__u8 kernel_mbox;
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#define VOYAGER_MAILBOX_VERSION 0x10
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__u8 SUS_version;
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__u8 kernel_version;
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#define VOYAGER_OS_HAS_SYSINT 0x1
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#define VOYAGER_OS_IN_PROGRESS 0x2
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#define VOYAGER_UPDATING_WDPERIOD 0x4
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__u32 kernel_flags;
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#define VOYAGER_SUS_BOOTING 0x1
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#define VOYAGER_SUS_IN_PROGRESS 0x2
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__u32 SUS_flags;
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__u32 watchdog_period;
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__u32 watchdog_count;
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__u32 SUS_errorlog;
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/* lots of system configuration stuff under here */
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};
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/* Variables exported by voyager_smp */
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extern __u32 voyager_extended_vic_processors;
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extern __u32 voyager_allowed_boot_processors;
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extern __u32 voyager_quad_processors;
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extern struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS];
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extern struct voyager_SUS *voyager_SUS;
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/* variables exported always */
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extern struct task_struct *voyager_thread;
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extern int voyager_level;
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extern struct voyager_status voyager_status;
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/* functions exported by the voyager and voyager_smp modules */
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extern int voyager_cat_readb(__u8 module, __u8 asic, int reg);
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extern void voyager_cat_init(void);
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extern void voyager_detect(struct voyager_bios_info *);
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extern void voyager_trap_init(void);
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extern void voyager_setup_irqs(void);
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extern int voyager_memory_detect(int region, __u32 *addr, __u32 *length);
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extern void voyager_smp_intr_init(void);
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extern __u8 voyager_extended_cmos_read(__u16 cmos_address);
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extern void voyager_smp_dump(void);
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extern void voyager_timer_interrupt(void);
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extern void smp_local_timer_interrupt(void);
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extern void voyager_power_off(void);
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extern void smp_voyager_power_off(void *dummy);
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extern void voyager_restart(void);
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extern void voyager_cat_power_off(void);
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extern void voyager_cat_do_common_interrupt(void);
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extern void voyager_handle_nmi(void);
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/* Commands for the following are */
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#define VOYAGER_PSI_READ 0
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#define VOYAGER_PSI_WRITE 1
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#define VOYAGER_PSI_SUBREAD 2
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#define VOYAGER_PSI_SUBWRITE 3
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extern void voyager_cat_psi(__u8, __u16, __u8 *);
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