7a9fd14d4c
Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
472 lines
12 KiB
C
472 lines
12 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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* Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_irq.h>
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static u32 irq_stat_addr[2];
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static u32 irq_mask_addr[2];
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static void (*dispatch_internal)(int cpu);
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static int is_ext_irq_cascaded;
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static unsigned int ext_irq_count;
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static unsigned int ext_irq_start, ext_irq_end;
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static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
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static void (*internal_irq_mask)(unsigned int irq);
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static void (*internal_irq_unmask)(unsigned int irq);
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static inline u32 get_ext_irq_perf_reg(int irq)
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{
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if (irq < 4)
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return ext_irq_cfg_reg1;
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return ext_irq_cfg_reg2;
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}
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static inline void handle_internal(int intbit)
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{
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if (is_ext_irq_cascaded &&
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intbit >= ext_irq_start && intbit <= ext_irq_end)
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do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
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else
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do_IRQ(intbit + IRQ_INTERNAL_BASE);
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}
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/*
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* dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
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* prioritize any interrupt relatively to another. the static counter
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* will resume the loop where it ended the last time we left this
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* function.
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*/
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#define BUILD_IPIC_INTERNAL(width) \
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void __dispatch_internal_##width(int cpu) \
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{ \
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u32 pending[width / 32]; \
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unsigned int src, tgt; \
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bool irqs_pending = false; \
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static unsigned int i[2]; \
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unsigned int *next = &i[cpu]; \
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\
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/* read registers in reverse order */ \
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for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
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u32 val; \
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\
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val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \
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val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \
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pending[--tgt] = val; \
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\
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if (val) \
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irqs_pending = true; \
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} \
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\
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if (!irqs_pending) \
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return; \
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\
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while (1) { \
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unsigned int to_call = *next; \
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\
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*next = (*next + 1) & (width - 1); \
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if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
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handle_internal(to_call); \
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break; \
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} \
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} \
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} \
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\
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static void __internal_irq_mask_##width(unsigned int irq) \
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{ \
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u32 val; \
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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\
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val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
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val &= ~(1 << bit); \
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bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
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} \
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\
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static void __internal_irq_unmask_##width(unsigned int irq) \
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{ \
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u32 val; \
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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\
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val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
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val |= (1 << bit); \
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bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
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}
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BUILD_IPIC_INTERNAL(32);
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BUILD_IPIC_INTERNAL(64);
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asmlinkage void plat_irq_dispatch(void)
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{
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u32 cause;
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do {
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cause = read_c0_cause() & read_c0_status() & ST0_IM;
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if (!cause)
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break;
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if (cause & CAUSEF_IP7)
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do_IRQ(7);
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if (cause & CAUSEF_IP0)
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do_IRQ(0);
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if (cause & CAUSEF_IP1)
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do_IRQ(1);
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if (cause & CAUSEF_IP2)
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dispatch_internal(0);
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if (!is_ext_irq_cascaded) {
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if (cause & CAUSEF_IP3)
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do_IRQ(IRQ_EXT_0);
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if (cause & CAUSEF_IP4)
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do_IRQ(IRQ_EXT_1);
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if (cause & CAUSEF_IP5)
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do_IRQ(IRQ_EXT_2);
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if (cause & CAUSEF_IP6)
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do_IRQ(IRQ_EXT_3);
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}
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} while (1);
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}
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/*
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* internal IRQs operations: only mask/unmask on PERF irq mask
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* register.
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*/
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static void bcm63xx_internal_irq_mask(struct irq_data *d)
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{
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internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
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}
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static void bcm63xx_internal_irq_unmask(struct irq_data *d)
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{
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internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
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}
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/*
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* external IRQs operations: mask/unmask and clear on PERF external
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* irq control register.
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*/
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static void bcm63xx_external_irq_mask(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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regaddr = get_ext_irq_perf_reg(irq);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
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else
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reg &= ~EXTIRQ_CFG_MASK(irq % 4);
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bcm_perf_writel(reg, regaddr);
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if (is_ext_irq_cascaded)
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internal_irq_mask(irq + ext_irq_start);
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}
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static void bcm63xx_external_irq_unmask(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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regaddr = get_ext_irq_perf_reg(irq);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
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else
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reg |= EXTIRQ_CFG_MASK(irq % 4);
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bcm_perf_writel(reg, regaddr);
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if (is_ext_irq_cascaded)
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internal_irq_unmask(irq + ext_irq_start);
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}
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static void bcm63xx_external_irq_clear(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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regaddr = get_ext_irq_perf_reg(irq);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
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else
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reg |= EXTIRQ_CFG_CLEAR(irq % 4);
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bcm_perf_writel(reg, regaddr);
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}
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static int bcm63xx_external_irq_set_type(struct irq_data *d,
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unsigned int flow_type)
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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int levelsense, sense, bothedge;
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flow_type &= IRQ_TYPE_SENSE_MASK;
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if (flow_type == IRQ_TYPE_NONE)
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flow_type = IRQ_TYPE_LEVEL_LOW;
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levelsense = sense = bothedge = 0;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_BOTH:
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bothedge = 1;
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break;
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case IRQ_TYPE_EDGE_RISING:
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sense = 1;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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levelsense = 1;
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sense = 1;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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levelsense = 1;
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break;
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default:
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printk(KERN_ERR "bogus flow type combination given !\n");
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return -EINVAL;
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}
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regaddr = get_ext_irq_perf_reg(irq);
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reg = bcm_perf_readl(regaddr);
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irq %= 4;
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switch (bcm63xx_get_cpu_id()) {
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case BCM6348_CPU_ID:
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if (levelsense)
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reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
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else
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reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
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if (sense)
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reg |= EXTIRQ_CFG_SENSE_6348(irq);
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else
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reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
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if (bothedge)
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reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
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else
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reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
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break;
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case BCM3368_CPU_ID:
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case BCM6328_CPU_ID:
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case BCM6338_CPU_ID:
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case BCM6345_CPU_ID:
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case BCM6358_CPU_ID:
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case BCM6362_CPU_ID:
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case BCM6368_CPU_ID:
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if (levelsense)
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reg |= EXTIRQ_CFG_LEVELSENSE(irq);
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else
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reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
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if (sense)
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reg |= EXTIRQ_CFG_SENSE(irq);
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else
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reg &= ~EXTIRQ_CFG_SENSE(irq);
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if (bothedge)
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reg |= EXTIRQ_CFG_BOTHEDGE(irq);
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else
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reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
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break;
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default:
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BUG();
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}
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bcm_perf_writel(reg, regaddr);
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irqd_set_trigger_type(d, flow_type);
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if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(d->irq, handle_level_irq);
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else
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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return IRQ_SET_MASK_OK_NOCOPY;
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}
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static struct irq_chip bcm63xx_internal_irq_chip = {
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.name = "bcm63xx_ipic",
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.irq_mask = bcm63xx_internal_irq_mask,
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.irq_unmask = bcm63xx_internal_irq_unmask,
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};
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static struct irq_chip bcm63xx_external_irq_chip = {
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.name = "bcm63xx_epic",
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.irq_ack = bcm63xx_external_irq_clear,
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.irq_mask = bcm63xx_external_irq_mask,
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.irq_unmask = bcm63xx_external_irq_unmask,
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.irq_set_type = bcm63xx_external_irq_set_type,
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};
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static struct irqaction cpu_ip2_cascade_action = {
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.handler = no_action,
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.name = "cascade_ip2",
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.flags = IRQF_NO_THREAD,
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};
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static struct irqaction cpu_ext_cascade_action = {
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.handler = no_action,
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.name = "cascade_extirq",
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.flags = IRQF_NO_THREAD,
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};
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static void bcm63xx_init_irq(void)
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{
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int irq_bits;
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irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
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irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
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irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
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irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
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switch (bcm63xx_get_cpu_id()) {
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case BCM3368_CPU_ID:
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irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
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irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
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irq_stat_addr[1] = 0;
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irq_stat_addr[1] = 0;
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irq_bits = 32;
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ext_irq_count = 4;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
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break;
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case BCM6328_CPU_ID:
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irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
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irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
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irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);
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irq_stat_addr[1] += PERF_IRQMASK_6328_REG(1);
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irq_bits = 64;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
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break;
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case BCM6338_CPU_ID:
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irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
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irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
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irq_stat_addr[1] = 0;
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irq_mask_addr[1] = 0;
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irq_bits = 32;
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ext_irq_count = 4;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
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break;
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case BCM6345_CPU_ID:
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irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
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irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
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irq_stat_addr[1] = 0;
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irq_mask_addr[1] = 0;
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irq_bits = 32;
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ext_irq_count = 4;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
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break;
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case BCM6348_CPU_ID:
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irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
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irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
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irq_stat_addr[1] = 0;
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irq_mask_addr[1] = 0;
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irq_bits = 32;
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ext_irq_count = 4;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
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break;
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case BCM6358_CPU_ID:
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irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
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irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
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irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1);
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irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);
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irq_bits = 32;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
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break;
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case BCM6362_CPU_ID:
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irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
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irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
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irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1);
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irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);
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irq_bits = 64;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
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break;
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case BCM6368_CPU_ID:
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irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
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irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
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irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
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irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
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irq_bits = 64;
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ext_irq_count = 6;
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is_ext_irq_cascaded = 1;
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ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
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ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
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break;
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default:
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BUG();
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}
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if (irq_bits == 32) {
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dispatch_internal = __dispatch_internal_32;
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internal_irq_mask = __internal_irq_mask_32;
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internal_irq_unmask = __internal_irq_unmask_32;
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} else {
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dispatch_internal = __dispatch_internal_64;
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internal_irq_mask = __internal_irq_mask_64;
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internal_irq_unmask = __internal_irq_unmask_64;
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}
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}
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void __init arch_init_irq(void)
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{
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int i;
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bcm63xx_init_irq();
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mips_cpu_irq_init();
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for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
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irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
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handle_level_irq);
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for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
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irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
|
|
handle_edge_irq);
|
|
|
|
if (!is_ext_irq_cascaded) {
|
|
for (i = 3; i < 3 + ext_irq_count; ++i)
|
|
setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
|
|
}
|
|
|
|
setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
|
|
}
|