tmp_suning_uos_patched/arch/xtensa
Max Filippov 19f6dcb1f0 xtensa: fix a7 clobbering in coprocessor context load/store
commit 839769c35477d4acc2369e45000ca7b0b6af39a7 upstream.

Fast coprocessor exception handler saves a3..a6, but coprocessor context
load/store code uses a4..a7 as temporaries, potentially clobbering a7.
'Potentially' because coprocessor state load/store macros may not use
all four temporary registers (and neither FPU nor HiFi macros do).
Use a3..a6 as intended.

Cc: stable@vger.kernel.org
Fixes: c658eac628 ("[XTENSA] Add support for configurable registers and coprocessors")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-04-27 13:53:55 +02:00
..
boot xtensa: fix DTC warning unit_address_format 2022-04-13 21:01:00 +02:00
configs
include xtensa: fix xtensa_wsr always writing 0 2022-04-08 14:39:58 +02:00
kernel xtensa: fix a7 clobbering in coprocessor context load/store 2022-04-27 13:53:55 +02:00
lib
mm
oprofile
platforms
variants
Kconfig
Kconfig.debug
Makefile