9a8fd55899
The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
33 lines
889 B
C
33 lines
889 B
C
/*
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* include/asm-xtensa/cacheflush.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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* 2 of the License, or (at your option) any later version.
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*
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* (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_CACHE_H
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#define _XTENSA_CACHE_H
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#include <xtensa/config/core.h>
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#if XCHAL_ICACHE_SIZE > 0
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# if (XCHAL_ICACHE_SIZE % (XCHAL_ICACHE_LINESIZE*XCHAL_ICACHE_WAYS*4)) != 0
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# error cache configuration outside expected/supported range!
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# endif
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#endif
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#if XCHAL_DCACHE_SIZE > 0
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# if (XCHAL_DCACHE_SIZE % (XCHAL_DCACHE_LINESIZE*XCHAL_DCACHE_WAYS*4)) != 0
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# error cache configuration outside expected/supported range!
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# endif
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#endif
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#define L1_CACHE_SHIFT XCHAL_CACHE_LINEWIDTH_MAX
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#define L1_CACHE_BYTES XCHAL_CACHE_LINESIZE_MAX
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#endif /* _XTENSA_CACHE_H */
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