09ec1d7ea6
This patch is for just moving plat-s3c24xx/*.c into mach-s3c24xx/, so that we could remove plat-s3c24xx directory. But since the PLAT_S3C24XX is used in drivers, the statement is not deleted and it will be sorted out next time. Cc: Ben Dooks <ben-linux@fluff.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
823 lines
25 KiB
C
823 lines
25 KiB
C
/*
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* S3C24XX IRQ handling
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*
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* Copyright (c) 2003-2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/irqdomain.h>
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#include <asm/mach/irq.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/regs-irqtype.h>
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#include <plat/pm.h>
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#include <plat/irq.h>
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#define S3C_IRQTYPE_NONE 0
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#define S3C_IRQTYPE_EINT 1
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#define S3C_IRQTYPE_EDGE 2
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#define S3C_IRQTYPE_LEVEL 3
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struct s3c_irq_data {
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unsigned int type;
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unsigned long parent_irq;
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/* data gets filled during init */
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struct s3c_irq_intc *intc;
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unsigned long sub_bits;
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struct s3c_irq_intc *sub_intc;
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};
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/*
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* Sructure holding the controller data
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* @reg_pending register holding pending irqs
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* @reg_intpnd special register intpnd in main intc
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* @reg_mask mask register
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* @domain irq_domain of the controller
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* @parent parent controller for ext and sub irqs
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* @irqs irq-data, always s3c_irq_data[32]
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*/
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struct s3c_irq_intc {
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void __iomem *reg_pending;
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void __iomem *reg_intpnd;
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void __iomem *reg_mask;
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struct irq_domain *domain;
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struct s3c_irq_intc *parent;
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struct s3c_irq_data *irqs;
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};
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static void s3c_irq_mask(struct irq_data *data)
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{
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struct s3c_irq_intc *intc = data->domain->host_data;
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struct s3c_irq_intc *parent_intc = intc->parent;
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struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
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struct s3c_irq_data *parent_data;
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unsigned long mask;
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unsigned int irqno;
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mask = __raw_readl(intc->reg_mask);
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mask |= (1UL << data->hwirq);
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__raw_writel(mask, intc->reg_mask);
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if (parent_intc && irq_data->parent_irq) {
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parent_data = &parent_intc->irqs[irq_data->parent_irq];
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/* check to see if we need to mask the parent IRQ */
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if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
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irqno = irq_find_mapping(parent_intc->domain,
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irq_data->parent_irq);
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s3c_irq_mask(irq_get_irq_data(irqno));
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}
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}
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}
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static void s3c_irq_unmask(struct irq_data *data)
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{
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struct s3c_irq_intc *intc = data->domain->host_data;
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struct s3c_irq_intc *parent_intc = intc->parent;
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struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
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unsigned long mask;
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unsigned int irqno;
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mask = __raw_readl(intc->reg_mask);
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mask &= ~(1UL << data->hwirq);
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__raw_writel(mask, intc->reg_mask);
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if (parent_intc && irq_data->parent_irq) {
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irqno = irq_find_mapping(parent_intc->domain,
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irq_data->parent_irq);
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s3c_irq_unmask(irq_get_irq_data(irqno));
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}
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}
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static inline void s3c_irq_ack(struct irq_data *data)
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{
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struct s3c_irq_intc *intc = data->domain->host_data;
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unsigned long bitval = 1UL << data->hwirq;
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__raw_writel(bitval, intc->reg_pending);
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if (intc->reg_intpnd)
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__raw_writel(bitval, intc->reg_intpnd);
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}
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static int s3c_irqext_type_set(void __iomem *gpcon_reg,
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void __iomem *extint_reg,
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unsigned long gpcon_offset,
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unsigned long extint_offset,
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unsigned int type)
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{
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unsigned long newvalue = 0, value;
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/* Set the GPIO to external interrupt mode */
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value = __raw_readl(gpcon_reg);
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value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
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__raw_writel(value, gpcon_reg);
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/* Set the external interrupt to pointed trigger type */
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switch (type)
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{
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case IRQ_TYPE_NONE:
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pr_warn("No edge setting!\n");
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break;
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case IRQ_TYPE_EDGE_RISING:
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newvalue = S3C2410_EXTINT_RISEEDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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newvalue = S3C2410_EXTINT_FALLEDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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newvalue = S3C2410_EXTINT_BOTHEDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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newvalue = S3C2410_EXTINT_LOWLEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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newvalue = S3C2410_EXTINT_HILEV;
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break;
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default:
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pr_err("No such irq type %d", type);
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return -EINVAL;
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}
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value = __raw_readl(extint_reg);
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value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
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__raw_writel(value, extint_reg);
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return 0;
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}
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/* FIXME: make static when it's out of plat-samsung/irq.h */
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int s3c_irqext_type(struct irq_data *data, unsigned int type)
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{
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void __iomem *extint_reg;
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void __iomem *gpcon_reg;
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unsigned long gpcon_offset, extint_offset;
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if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
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gpcon_reg = S3C2410_GPFCON;
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extint_reg = S3C24XX_EXTINT0;
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gpcon_offset = (data->hwirq) * 2;
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extint_offset = (data->hwirq) * 4;
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} else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
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gpcon_reg = S3C2410_GPGCON;
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extint_reg = S3C24XX_EXTINT1;
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gpcon_offset = (data->hwirq - 8) * 2;
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extint_offset = (data->hwirq - 8) * 4;
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} else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
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gpcon_reg = S3C2410_GPGCON;
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extint_reg = S3C24XX_EXTINT2;
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gpcon_offset = (data->hwirq - 8) * 2;
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extint_offset = (data->hwirq - 16) * 4;
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} else {
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return -EINVAL;
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}
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return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
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extint_offset, type);
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}
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static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
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{
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void __iomem *extint_reg;
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void __iomem *gpcon_reg;
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unsigned long gpcon_offset, extint_offset;
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if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
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gpcon_reg = S3C2410_GPFCON;
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extint_reg = S3C24XX_EXTINT0;
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gpcon_offset = (data->hwirq) * 2;
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extint_offset = (data->hwirq) * 4;
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} else {
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return -EINVAL;
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}
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return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
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extint_offset, type);
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}
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struct irq_chip s3c_irq_chip = {
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.name = "s3c",
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.irq_ack = s3c_irq_ack,
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.irq_mask = s3c_irq_mask,
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.irq_unmask = s3c_irq_unmask,
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.irq_set_wake = s3c_irq_wake
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};
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struct irq_chip s3c_irq_level_chip = {
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.name = "s3c-level",
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.irq_mask = s3c_irq_mask,
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.irq_unmask = s3c_irq_unmask,
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.irq_ack = s3c_irq_ack,
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};
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static struct irq_chip s3c_irqext_chip = {
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.name = "s3c-ext",
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.irq_mask = s3c_irq_mask,
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.irq_unmask = s3c_irq_unmask,
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.irq_ack = s3c_irq_ack,
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.irq_set_type = s3c_irqext_type,
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.irq_set_wake = s3c_irqext_wake
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};
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static struct irq_chip s3c_irq_eint0t4 = {
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.name = "s3c-ext0",
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.irq_ack = s3c_irq_ack,
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.irq_mask = s3c_irq_mask,
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.irq_unmask = s3c_irq_unmask,
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.irq_set_wake = s3c_irq_wake,
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.irq_set_type = s3c_irqext0_type,
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};
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static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
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struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
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struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
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unsigned long src;
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unsigned long msk;
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unsigned int n;
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chained_irq_enter(chip, desc);
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src = __raw_readl(sub_intc->reg_pending);
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msk = __raw_readl(sub_intc->reg_mask);
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src &= ~msk;
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src &= irq_data->sub_bits;
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while (src) {
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n = __ffs(src);
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src &= ~(1 << n);
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generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
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}
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chained_irq_exit(chip, desc);
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}
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#ifdef CONFIG_FIQ
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/**
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* s3c24xx_set_fiq - set the FIQ routing
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* @irq: IRQ number to route to FIQ on processor.
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* @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
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*
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* Change the state of the IRQ to FIQ routing depending on @irq and @on. If
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* @on is true, the @irq is checked to see if it can be routed and the
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* interrupt controller updated to route the IRQ. If @on is false, the FIQ
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* routing is cleared, regardless of which @irq is specified.
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*/
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int s3c24xx_set_fiq(unsigned int irq, bool on)
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{
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u32 intmod;
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unsigned offs;
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if (on) {
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offs = irq - FIQ_START;
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if (offs > 31)
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return -EINVAL;
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intmod = 1 << offs;
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} else {
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intmod = 0;
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}
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__raw_writel(intmod, S3C2410_INTMOD);
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return 0;
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}
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EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
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#endif
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static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct s3c_irq_intc *intc = h->host_data;
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struct s3c_irq_data *irq_data = &intc->irqs[hw];
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struct s3c_irq_intc *parent_intc;
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struct s3c_irq_data *parent_irq_data;
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unsigned int irqno;
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if (!intc) {
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pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
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return -EINVAL;
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}
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if (!irq_data) {
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pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
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return -EINVAL;
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}
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/* attach controller pointer to irq_data */
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irq_data->intc = intc;
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/* set handler and flags */
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switch (irq_data->type) {
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case S3C_IRQTYPE_NONE:
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return 0;
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case S3C_IRQTYPE_EINT:
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if (irq_data->parent_irq)
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irq_set_chip_and_handler(virq, &s3c_irqext_chip,
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handle_edge_irq);
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else
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irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
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handle_edge_irq);
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break;
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case S3C_IRQTYPE_EDGE:
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if (irq_data->parent_irq ||
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intc->reg_pending == S3C2416_SRCPND2)
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irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
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handle_edge_irq);
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else
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irq_set_chip_and_handler(virq, &s3c_irq_chip,
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handle_edge_irq);
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break;
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case S3C_IRQTYPE_LEVEL:
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if (irq_data->parent_irq)
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irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
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handle_level_irq);
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else
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irq_set_chip_and_handler(virq, &s3c_irq_chip,
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handle_level_irq);
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break;
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default:
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pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
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return -EINVAL;
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}
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set_irq_flags(virq, IRQF_VALID);
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if (irq_data->parent_irq) {
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parent_intc = intc->parent;
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if (!parent_intc) {
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pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
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hw);
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goto err;
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}
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parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
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if (!irq_data) {
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pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
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hw);
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goto err;
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}
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parent_irq_data->sub_intc = intc;
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parent_irq_data->sub_bits |= (1UL << hw);
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/* attach the demuxer to the parent irq */
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irqno = irq_find_mapping(parent_intc->domain,
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irq_data->parent_irq);
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if (!irqno) {
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pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
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irq_data->parent_irq);
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goto err;
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}
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irq_set_chained_handler(irqno, s3c_irq_demux);
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}
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return 0;
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err:
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set_irq_flags(virq, 0);
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/* the only error can result from bad mapping data*/
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return -EINVAL;
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}
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static struct irq_domain_ops s3c24xx_irq_ops = {
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.map = s3c24xx_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
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{
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void __iomem *reg_source;
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unsigned long pend;
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unsigned long last;
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int i;
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/* if intpnd is set, read the next pending irq from there */
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reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
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last = 0;
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for (i = 0; i < 4; i++) {
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pend = __raw_readl(reg_source);
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if (pend == 0 || pend == last)
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break;
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__raw_writel(pend, intc->reg_pending);
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if (intc->reg_intpnd)
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__raw_writel(pend, intc->reg_intpnd);
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pr_info("irq: clearing pending status %08x\n", (int)pend);
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last = pend;
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}
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}
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struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
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struct s3c_irq_data *irq_data,
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struct s3c_irq_intc *parent,
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unsigned long address)
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{
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struct s3c_irq_intc *intc;
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void __iomem *base = (void *)0xf6000000; /* static mapping */
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int irq_num;
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int irq_start;
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int irq_offset;
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int ret;
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intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
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if (!intc)
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return ERR_PTR(-ENOMEM);
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intc->irqs = irq_data;
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|
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if (parent)
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intc->parent = parent;
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|
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/* select the correct data for the controller.
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* Need to hard code the irq num start and offset
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* to preserve the static mapping for now
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*/
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switch (address) {
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case 0x4a000000:
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pr_debug("irq: found main intc\n");
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intc->reg_pending = base;
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intc->reg_mask = base + 0x08;
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intc->reg_intpnd = base + 0x10;
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irq_num = 32;
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irq_start = S3C2410_IRQ(0);
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irq_offset = 0;
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break;
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case 0x4a000018:
|
|
pr_debug("irq: found subintc\n");
|
|
intc->reg_pending = base + 0x18;
|
|
intc->reg_mask = base + 0x1c;
|
|
irq_num = 29;
|
|
irq_start = S3C2410_IRQSUB(0);
|
|
irq_offset = 0;
|
|
break;
|
|
case 0x4a000040:
|
|
pr_debug("irq: found intc2\n");
|
|
intc->reg_pending = base + 0x40;
|
|
intc->reg_mask = base + 0x48;
|
|
intc->reg_intpnd = base + 0x50;
|
|
irq_num = 8;
|
|
irq_start = S3C2416_IRQ(0);
|
|
irq_offset = 0;
|
|
break;
|
|
case 0x560000a4:
|
|
pr_debug("irq: found eintc\n");
|
|
base = (void *)0xfd000000;
|
|
|
|
intc->reg_mask = base + 0xa4;
|
|
intc->reg_pending = base + 0x08;
|
|
irq_num = 20;
|
|
irq_start = S3C2410_IRQ(32);
|
|
irq_offset = 4;
|
|
break;
|
|
default:
|
|
pr_err("irq: unsupported controller address\n");
|
|
ret = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
/* now that all the data is complete, init the irq-domain */
|
|
s3c24xx_clear_intc(intc);
|
|
intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
|
|
irq_offset, &s3c24xx_irq_ops,
|
|
intc);
|
|
if (!intc->domain) {
|
|
pr_err("irq: could not create irq-domain\n");
|
|
ret = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
return intc;
|
|
|
|
err:
|
|
kfree(intc);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
/* s3c24xx_init_irq
|
|
*
|
|
* Initialise S3C2410 IRQ system
|
|
*/
|
|
|
|
static struct s3c_irq_data init_base[32] = {
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TICK */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* WDT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* LCD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBH */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* IIC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* RTC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
|
|
};
|
|
|
|
static struct s3c_irq_data init_eint[32] = {
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
|
|
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
|
|
};
|
|
|
|
static struct s3c_irq_data init_subint[32] = {
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
|
|
};
|
|
|
|
void __init s3c24xx_init_irq(void)
|
|
{
|
|
struct s3c_irq_intc *main_intc;
|
|
|
|
#ifdef CONFIG_FIQ
|
|
init_FIQ(FIQ_START);
|
|
#endif
|
|
|
|
main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
|
|
if (IS_ERR(main_intc)) {
|
|
pr_err("irq: could not create main interrupt controller\n");
|
|
return;
|
|
}
|
|
|
|
s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
|
|
s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_S3C2416
|
|
static struct s3c_irq_data init_s3c2416base[32] = {
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TICK */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
|
|
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* NAND */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBH */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* IIC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
|
|
{ .type = S3C_IRQTYPE_NONE, },
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* RTC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
|
|
};
|
|
|
|
static struct s3c_irq_data init_s3c2416subint[32] = {
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
|
|
};
|
|
|
|
static struct s3c_irq_data init_s3c2416_second[32] = {
|
|
{ .type = S3C_IRQTYPE_EDGE }, /* 2D */
|
|
{ .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
|
|
{ .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
|
|
{ .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
|
|
{ .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
|
|
};
|
|
|
|
void __init s3c2416_init_irq(void)
|
|
{
|
|
struct s3c_irq_intc *main_intc;
|
|
|
|
pr_info("S3C2416: IRQ Support\n");
|
|
|
|
#ifdef CONFIG_FIQ
|
|
init_FIQ(FIQ_START);
|
|
#endif
|
|
|
|
main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
|
|
if (IS_ERR(main_intc)) {
|
|
pr_err("irq: could not create main interrupt controller\n");
|
|
return;
|
|
}
|
|
|
|
s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
|
|
s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
|
|
|
|
s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_S3C2443
|
|
static struct s3c_irq_data init_s3c2443base[32] = {
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
|
|
{ .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TICK */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* CFON */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* NAND */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* USBH */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* IIC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
|
|
{ .type = S3C_IRQTYPE_EDGE, }, /* RTC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
|
|
};
|
|
|
|
|
|
static struct s3c_irq_data init_s3c2443subint[32] = {
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
|
|
{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
|
|
{ .type = S3C_IRQTYPE_NONE }, /* reserved */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
|
|
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
|
|
};
|
|
|
|
void __init s3c2443_init_irq(void)
|
|
{
|
|
struct s3c_irq_intc *main_intc;
|
|
|
|
pr_info("S3C2443: IRQ Support\n");
|
|
|
|
#ifdef CONFIG_FIQ
|
|
init_FIQ(FIQ_START);
|
|
#endif
|
|
|
|
main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
|
|
if (IS_ERR(main_intc)) {
|
|
pr_err("irq: could not create main interrupt controller\n");
|
|
return;
|
|
}
|
|
|
|
s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
|
|
s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
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}
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#endif
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