223d47278a
This patch updates the name identifier to list both of the Marvell PHYs that are supported. Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
662 lines
16 KiB
C
662 lines
16 KiB
C
/*
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* drivers/net/gianfar_phy.c
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*
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* Gianfar Ethernet Driver -- PHY handling
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* Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
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* Based on 8260_io/fcc_enet.c
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*
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* Author: Andy Fleming
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* Maintainer: Kumar Gala (kumar.gala@freescale.com)
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*
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* Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <linux/module.h>
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#include <linux/version.h>
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#include <linux/crc32.h>
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#include <linux/mii.h>
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#include "gianfar.h"
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#include "gianfar_phy.h"
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static void config_genmii_advert(struct gfar_mii_info *mii_info);
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static void genmii_setup_forced(struct gfar_mii_info *mii_info);
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static void genmii_restart_aneg(struct gfar_mii_info *mii_info);
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static int gbit_config_aneg(struct gfar_mii_info *mii_info);
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static int genmii_config_aneg(struct gfar_mii_info *mii_info);
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static int genmii_update_link(struct gfar_mii_info *mii_info);
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static int genmii_read_status(struct gfar_mii_info *mii_info);
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u16 phy_read(struct gfar_mii_info *mii_info, u16 regnum);
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void phy_write(struct gfar_mii_info *mii_info, u16 regnum, u16 val);
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/* Write value to the PHY for this device to the register at regnum, */
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/* waiting until the write is done before it returns. All PHY */
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/* configuration has to be done through the TSEC1 MIIM regs */
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void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value)
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{
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struct gfar_private *priv = netdev_priv(dev);
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struct gfar *regbase = priv->phyregs;
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/* Set the PHY address and the register address we want to write */
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gfar_write(®base->miimadd, (mii_id << 8) | regnum);
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/* Write out the value we want */
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gfar_write(®base->miimcon, value);
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/* Wait for the transaction to finish */
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while (gfar_read(®base->miimind) & MIIMIND_BUSY)
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cpu_relax();
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}
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/* Reads from register regnum in the PHY for device dev, */
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/* returning the value. Clears miimcom first. All PHY */
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/* configuration has to be done through the TSEC1 MIIM regs */
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int read_phy_reg(struct net_device *dev, int mii_id, int regnum)
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{
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struct gfar_private *priv = netdev_priv(dev);
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struct gfar *regbase = priv->phyregs;
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u16 value;
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/* Set the PHY address and the register address we want to read */
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gfar_write(®base->miimadd, (mii_id << 8) | regnum);
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/* Clear miimcom, and then initiate a read */
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gfar_write(®base->miimcom, 0);
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gfar_write(®base->miimcom, MII_READ_COMMAND);
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/* Wait for the transaction to finish */
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while (gfar_read(®base->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
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cpu_relax();
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/* Grab the value of the register from miimstat */
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value = gfar_read(®base->miimstat);
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return value;
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}
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void mii_clear_phy_interrupt(struct gfar_mii_info *mii_info)
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{
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if(mii_info->phyinfo->ack_interrupt)
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mii_info->phyinfo->ack_interrupt(mii_info);
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}
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void mii_configure_phy_interrupt(struct gfar_mii_info *mii_info, u32 interrupts)
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{
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mii_info->interrupts = interrupts;
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if(mii_info->phyinfo->config_intr)
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mii_info->phyinfo->config_intr(mii_info);
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}
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/* Writes MII_ADVERTISE with the appropriate values, after
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* sanitizing advertise to make sure only supported features
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* are advertised
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*/
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static void config_genmii_advert(struct gfar_mii_info *mii_info)
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{
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u32 advertise;
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u16 adv;
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/* Only allow advertising what this PHY supports */
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mii_info->advertising &= mii_info->phyinfo->features;
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advertise = mii_info->advertising;
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/* Setup standard advertisement */
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adv = phy_read(mii_info, MII_ADVERTISE);
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adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
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if (advertise & ADVERTISED_10baseT_Half)
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adv |= ADVERTISE_10HALF;
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if (advertise & ADVERTISED_10baseT_Full)
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adv |= ADVERTISE_10FULL;
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if (advertise & ADVERTISED_100baseT_Half)
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adv |= ADVERTISE_100HALF;
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if (advertise & ADVERTISED_100baseT_Full)
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adv |= ADVERTISE_100FULL;
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phy_write(mii_info, MII_ADVERTISE, adv);
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}
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static void genmii_setup_forced(struct gfar_mii_info *mii_info)
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{
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u16 ctrl;
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u32 features = mii_info->phyinfo->features;
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ctrl = phy_read(mii_info, MII_BMCR);
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ctrl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPEED1000|BMCR_ANENABLE);
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ctrl |= BMCR_RESET;
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switch(mii_info->speed) {
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case SPEED_1000:
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if(features & (SUPPORTED_1000baseT_Half
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| SUPPORTED_1000baseT_Full)) {
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ctrl |= BMCR_SPEED1000;
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break;
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}
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mii_info->speed = SPEED_100;
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case SPEED_100:
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if (features & (SUPPORTED_100baseT_Half
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| SUPPORTED_100baseT_Full)) {
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ctrl |= BMCR_SPEED100;
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break;
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}
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mii_info->speed = SPEED_10;
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case SPEED_10:
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if (features & (SUPPORTED_10baseT_Half
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| SUPPORTED_10baseT_Full))
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break;
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default: /* Unsupported speed! */
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printk(KERN_ERR "%s: Bad speed!\n",
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mii_info->dev->name);
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break;
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}
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phy_write(mii_info, MII_BMCR, ctrl);
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}
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/* Enable and Restart Autonegotiation */
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static void genmii_restart_aneg(struct gfar_mii_info *mii_info)
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{
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u16 ctl;
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ctl = phy_read(mii_info, MII_BMCR);
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ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
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phy_write(mii_info, MII_BMCR, ctl);
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}
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static int gbit_config_aneg(struct gfar_mii_info *mii_info)
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{
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u16 adv;
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u32 advertise;
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if(mii_info->autoneg) {
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/* Configure the ADVERTISE register */
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config_genmii_advert(mii_info);
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advertise = mii_info->advertising;
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adv = phy_read(mii_info, MII_1000BASETCONTROL);
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adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
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MII_1000BASETCONTROL_HALFDUPLEXCAP);
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if (advertise & SUPPORTED_1000baseT_Half)
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adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
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if (advertise & SUPPORTED_1000baseT_Full)
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adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
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phy_write(mii_info, MII_1000BASETCONTROL, adv);
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/* Start/Restart aneg */
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genmii_restart_aneg(mii_info);
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} else
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genmii_setup_forced(mii_info);
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return 0;
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}
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static int marvell_config_aneg(struct gfar_mii_info *mii_info)
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{
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/* The Marvell PHY has an errata which requires
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* that certain registers get written in order
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* to restart autonegotiation */
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phy_write(mii_info, MII_BMCR, BMCR_RESET);
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phy_write(mii_info, 0x1d, 0x1f);
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phy_write(mii_info, 0x1e, 0x200c);
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phy_write(mii_info, 0x1d, 0x5);
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phy_write(mii_info, 0x1e, 0);
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phy_write(mii_info, 0x1e, 0x100);
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gbit_config_aneg(mii_info);
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return 0;
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}
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static int genmii_config_aneg(struct gfar_mii_info *mii_info)
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{
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if (mii_info->autoneg) {
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config_genmii_advert(mii_info);
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genmii_restart_aneg(mii_info);
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} else
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genmii_setup_forced(mii_info);
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return 0;
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}
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static int genmii_update_link(struct gfar_mii_info *mii_info)
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{
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u16 status;
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/* Do a fake read */
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phy_read(mii_info, MII_BMSR);
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/* Read link and autonegotiation status */
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status = phy_read(mii_info, MII_BMSR);
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if ((status & BMSR_LSTATUS) == 0)
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mii_info->link = 0;
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else
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mii_info->link = 1;
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/* If we are autonegotiating, and not done,
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* return an error */
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if (mii_info->autoneg && !(status & BMSR_ANEGCOMPLETE))
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return -EAGAIN;
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return 0;
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}
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static int genmii_read_status(struct gfar_mii_info *mii_info)
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{
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u16 status;
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int err;
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/* Update the link, but return if there
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* was an error */
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err = genmii_update_link(mii_info);
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if (err)
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return err;
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if (mii_info->autoneg) {
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status = phy_read(mii_info, MII_LPA);
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if (status & (LPA_10FULL | LPA_100FULL))
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mii_info->duplex = DUPLEX_FULL;
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else
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mii_info->duplex = DUPLEX_HALF;
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if (status & (LPA_100FULL | LPA_100HALF))
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mii_info->speed = SPEED_100;
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else
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mii_info->speed = SPEED_10;
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mii_info->pause = 0;
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}
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/* On non-aneg, we assume what we put in BMCR is the speed,
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* though magic-aneg shouldn't prevent this case from occurring
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*/
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return 0;
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}
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static int marvell_read_status(struct gfar_mii_info *mii_info)
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{
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u16 status;
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int err;
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/* Update the link, but return if there
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* was an error */
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err = genmii_update_link(mii_info);
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if (err)
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return err;
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/* If the link is up, read the speed and duplex */
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/* If we aren't autonegotiating, assume speeds
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* are as set */
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if (mii_info->autoneg && mii_info->link) {
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int speed;
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status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
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#if 0
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/* If speed and duplex aren't resolved,
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* return an error. Isn't this handled
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* by checking aneg?
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*/
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if ((status & MII_M1011_PHY_SPEC_STATUS_RESOLVED) == 0)
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return -EAGAIN;
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#endif
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/* Get the duplexity */
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if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
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mii_info->duplex = DUPLEX_FULL;
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else
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mii_info->duplex = DUPLEX_HALF;
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/* Get the speed */
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speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
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switch(speed) {
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case MII_M1011_PHY_SPEC_STATUS_1000:
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mii_info->speed = SPEED_1000;
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break;
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case MII_M1011_PHY_SPEC_STATUS_100:
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mii_info->speed = SPEED_100;
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break;
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default:
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mii_info->speed = SPEED_10;
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break;
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}
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mii_info->pause = 0;
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}
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return 0;
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}
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static int cis820x_read_status(struct gfar_mii_info *mii_info)
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{
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u16 status;
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int err;
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/* Update the link, but return if there
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* was an error */
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err = genmii_update_link(mii_info);
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if (err)
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return err;
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/* If the link is up, read the speed and duplex */
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/* If we aren't autonegotiating, assume speeds
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* are as set */
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if (mii_info->autoneg && mii_info->link) {
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int speed;
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status = phy_read(mii_info, MII_CIS8201_AUX_CONSTAT);
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if (status & MII_CIS8201_AUXCONSTAT_DUPLEX)
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mii_info->duplex = DUPLEX_FULL;
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else
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mii_info->duplex = DUPLEX_HALF;
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speed = status & MII_CIS8201_AUXCONSTAT_SPEED;
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switch (speed) {
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case MII_CIS8201_AUXCONSTAT_GBIT:
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mii_info->speed = SPEED_1000;
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break;
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case MII_CIS8201_AUXCONSTAT_100:
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mii_info->speed = SPEED_100;
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break;
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default:
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mii_info->speed = SPEED_10;
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break;
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}
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}
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return 0;
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}
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static int marvell_ack_interrupt(struct gfar_mii_info *mii_info)
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{
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/* Clear the interrupts by reading the reg */
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phy_read(mii_info, MII_M1011_IEVENT);
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return 0;
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}
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static int marvell_config_intr(struct gfar_mii_info *mii_info)
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{
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if(mii_info->interrupts == MII_INTERRUPT_ENABLED)
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phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
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else
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phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
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return 0;
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}
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static int cis820x_init(struct gfar_mii_info *mii_info)
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{
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phy_write(mii_info, MII_CIS8201_AUX_CONSTAT,
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MII_CIS8201_AUXCONSTAT_INIT);
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phy_write(mii_info, MII_CIS8201_EXT_CON1,
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MII_CIS8201_EXTCON1_INIT);
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return 0;
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}
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static int cis820x_ack_interrupt(struct gfar_mii_info *mii_info)
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{
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phy_read(mii_info, MII_CIS8201_ISTAT);
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return 0;
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}
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static int cis820x_config_intr(struct gfar_mii_info *mii_info)
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{
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if(mii_info->interrupts == MII_INTERRUPT_ENABLED)
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phy_write(mii_info, MII_CIS8201_IMASK, MII_CIS8201_IMASK_MASK);
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else
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phy_write(mii_info, MII_CIS8201_IMASK, 0);
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return 0;
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}
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#define DM9161_DELAY 10
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static int dm9161_read_status(struct gfar_mii_info *mii_info)
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{
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u16 status;
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int err;
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/* Update the link, but return if there
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* was an error */
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err = genmii_update_link(mii_info);
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if (err)
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return err;
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/* If the link is up, read the speed and duplex */
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/* If we aren't autonegotiating, assume speeds
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* are as set */
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if (mii_info->autoneg && mii_info->link) {
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status = phy_read(mii_info, MII_DM9161_SCSR);
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if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
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mii_info->speed = SPEED_100;
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else
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mii_info->speed = SPEED_10;
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if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
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mii_info->duplex = DUPLEX_FULL;
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else
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mii_info->duplex = DUPLEX_HALF;
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}
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return 0;
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}
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static int dm9161_config_aneg(struct gfar_mii_info *mii_info)
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{
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struct dm9161_private *priv = mii_info->priv;
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if(0 == priv->resetdone)
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return -EAGAIN;
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return 0;
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}
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static void dm9161_timer(unsigned long data)
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{
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struct gfar_mii_info *mii_info = (struct gfar_mii_info *)data;
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struct dm9161_private *priv = mii_info->priv;
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u16 status = phy_read(mii_info, MII_BMSR);
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if (status & BMSR_ANEGCOMPLETE) {
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priv->resetdone = 1;
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} else
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mod_timer(&priv->timer, jiffies + DM9161_DELAY * HZ);
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}
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static int dm9161_init(struct gfar_mii_info *mii_info)
|
|
{
|
|
struct dm9161_private *priv;
|
|
|
|
/* Allocate the private data structure */
|
|
priv = kmalloc(sizeof(struct dm9161_private), GFP_KERNEL);
|
|
|
|
if (NULL == priv)
|
|
return -ENOMEM;
|
|
|
|
mii_info->priv = priv;
|
|
|
|
/* Reset is not done yet */
|
|
priv->resetdone = 0;
|
|
|
|
/* Isolate the PHY */
|
|
phy_write(mii_info, MII_BMCR, BMCR_ISOLATE);
|
|
|
|
/* Do not bypass the scrambler/descrambler */
|
|
phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
|
|
|
|
/* Clear 10BTCSR to default */
|
|
phy_write(mii_info, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT);
|
|
|
|
/* Reconnect the PHY, and enable Autonegotiation */
|
|
phy_write(mii_info, MII_BMCR, BMCR_ANENABLE);
|
|
|
|
/* Start a timer for DM9161_DELAY seconds to wait
|
|
* for the PHY to be ready */
|
|
init_timer(&priv->timer);
|
|
priv->timer.function = &dm9161_timer;
|
|
priv->timer.data = (unsigned long) mii_info;
|
|
mod_timer(&priv->timer, jiffies + DM9161_DELAY * HZ);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dm9161_close(struct gfar_mii_info *mii_info)
|
|
{
|
|
struct dm9161_private *priv = mii_info->priv;
|
|
|
|
del_timer_sync(&priv->timer);
|
|
kfree(priv);
|
|
}
|
|
|
|
#if 0
|
|
static int dm9161_ack_interrupt(struct gfar_mii_info *mii_info)
|
|
{
|
|
phy_read(mii_info, MII_DM9161_INTR);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/* Cicada 820x */
|
|
static struct phy_info phy_info_cis820x = {
|
|
0x000fc440,
|
|
"Cicada Cis8204",
|
|
0x000fffc0,
|
|
.features = MII_GBIT_FEATURES,
|
|
.init = &cis820x_init,
|
|
.config_aneg = &gbit_config_aneg,
|
|
.read_status = &cis820x_read_status,
|
|
.ack_interrupt = &cis820x_ack_interrupt,
|
|
.config_intr = &cis820x_config_intr,
|
|
};
|
|
|
|
static struct phy_info phy_info_dm9161 = {
|
|
.phy_id = 0x0181b880,
|
|
.name = "Davicom DM9161E",
|
|
.phy_id_mask = 0x0ffffff0,
|
|
.init = dm9161_init,
|
|
.config_aneg = dm9161_config_aneg,
|
|
.read_status = dm9161_read_status,
|
|
.close = dm9161_close,
|
|
};
|
|
|
|
static struct phy_info phy_info_marvell = {
|
|
.phy_id = 0x01410c00,
|
|
.phy_id_mask = 0xffffff00,
|
|
.name = "Marvell 88E1101/88E1111",
|
|
.features = MII_GBIT_FEATURES,
|
|
.config_aneg = &marvell_config_aneg,
|
|
.read_status = &marvell_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
};
|
|
|
|
static struct phy_info phy_info_genmii= {
|
|
.phy_id = 0x00000000,
|
|
.phy_id_mask = 0x00000000,
|
|
.name = "Generic MII",
|
|
.features = MII_BASIC_FEATURES,
|
|
.config_aneg = genmii_config_aneg,
|
|
.read_status = genmii_read_status,
|
|
};
|
|
|
|
static struct phy_info *phy_info[] = {
|
|
&phy_info_cis820x,
|
|
&phy_info_marvell,
|
|
&phy_info_dm9161,
|
|
&phy_info_genmii,
|
|
NULL
|
|
};
|
|
|
|
u16 phy_read(struct gfar_mii_info *mii_info, u16 regnum)
|
|
{
|
|
u16 retval;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&mii_info->mdio_lock, flags);
|
|
retval = mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
|
|
spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
|
|
|
|
return retval;
|
|
}
|
|
|
|
void phy_write(struct gfar_mii_info *mii_info, u16 regnum, u16 val)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&mii_info->mdio_lock, flags);
|
|
mii_info->mdio_write(mii_info->dev,
|
|
mii_info->mii_id,
|
|
regnum, val);
|
|
spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
|
|
}
|
|
|
|
/* Use the PHY ID registers to determine what type of PHY is attached
|
|
* to device dev. return a struct phy_info structure describing that PHY
|
|
*/
|
|
struct phy_info * get_phy_info(struct gfar_mii_info *mii_info)
|
|
{
|
|
u16 phy_reg;
|
|
u32 phy_ID;
|
|
int i;
|
|
struct phy_info *theInfo = NULL;
|
|
struct net_device *dev = mii_info->dev;
|
|
|
|
/* Grab the bits from PHYIR1, and put them in the upper half */
|
|
phy_reg = phy_read(mii_info, MII_PHYSID1);
|
|
phy_ID = (phy_reg & 0xffff) << 16;
|
|
|
|
/* Grab the bits from PHYIR2, and put them in the lower half */
|
|
phy_reg = phy_read(mii_info, MII_PHYSID2);
|
|
phy_ID |= (phy_reg & 0xffff);
|
|
|
|
/* loop through all the known PHY types, and find one that */
|
|
/* matches the ID we read from the PHY. */
|
|
for (i = 0; phy_info[i]; i++)
|
|
if (phy_info[i]->phy_id ==
|
|
(phy_ID & phy_info[i]->phy_id_mask)) {
|
|
theInfo = phy_info[i];
|
|
break;
|
|
}
|
|
|
|
/* This shouldn't happen, as we have generic PHY support */
|
|
if (theInfo == NULL) {
|
|
printk("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
|
|
return NULL;
|
|
} else {
|
|
printk("%s: PHY is %s (%x)\n", dev->name, theInfo->name,
|
|
phy_ID);
|
|
}
|
|
|
|
return theInfo;
|
|
}
|