1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
204 lines
4.2 KiB
ArmAsm
204 lines
4.2 KiB
ArmAsm
/*
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* arch/alpha/lib/ev6-copy_page.S
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*
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* Copy an entire page.
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*/
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/* The following comparison of this routine vs the normal copy_page.S
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was written by an unnamed ev6 hardware designer and forwarded to me
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via Steven Hobbs <hobbs@steven.zko.dec.com>.
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First Problem: STQ overflows.
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-----------------------------
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It would be nice if EV6 handled every resource overflow efficiently,
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but for some it doesn't. Including store queue overflows. It causes
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a trap and a restart of the pipe.
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To get around this we sometimes use (to borrow a term from a VSSAD
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researcher) "aeration". The idea is to slow the rate at which the
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processor receives valid instructions by inserting nops in the fetch
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path. In doing so, you can prevent the overflow and actually make
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the code run faster. You can, of course, take advantage of the fact
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that the processor can fetch at most 4 aligned instructions per cycle.
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I inserted enough nops to force it to take 10 cycles to fetch the
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loop code. In theory, EV6 should be able to execute this loop in
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9 cycles but I was not able to get it to run that fast -- the initial
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conditions were such that I could not reach this optimum rate on
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(chaotic) EV6. I wrote the code such that everything would issue
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in order.
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Second Problem: Dcache index matches.
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-------------------------------------
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If you are going to use this routine on random aligned pages, there
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is a 25% chance that the pages will be at the same dcache indices.
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This results in many nasty memory traps without care.
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The solution is to schedule the prefetches to avoid the memory
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conflicts. I schedule the wh64 prefetches farther ahead of the
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read prefetches to avoid this problem.
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Third Problem: Needs more prefetching.
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--------------------------------------
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In order to improve the code I added deeper prefetching to take the
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most advantage of EV6's bandwidth.
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I also prefetched the read stream. Note that adding the read prefetch
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forced me to add another cycle to the inner-most kernel - up to 11
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from the original 8 cycles per iteration. We could improve performance
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further by unrolling the loop and doing multiple prefetches per cycle.
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I think that the code below will be very robust and fast code for the
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purposes of copying aligned pages. It is slower when both source and
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destination pages are in the dcache, but it is my guess that this is
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less important than the dcache miss case. */
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.text
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.align 4
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.global copy_page
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.ent copy_page
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copy_page:
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.prologue 0
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/* Prefetch 5 read cachelines; write-hint 10 cache lines. */
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wh64 ($16)
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ldl $31,0($17)
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ldl $31,64($17)
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lda $1,1*64($16)
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wh64 ($1)
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ldl $31,128($17)
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ldl $31,192($17)
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lda $1,2*64($16)
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wh64 ($1)
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ldl $31,256($17)
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lda $18,118
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lda $1,3*64($16)
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wh64 ($1)
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nop
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lda $1,4*64($16)
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lda $2,5*64($16)
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wh64 ($1)
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wh64 ($2)
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lda $1,6*64($16)
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lda $2,7*64($16)
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wh64 ($1)
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wh64 ($2)
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lda $1,8*64($16)
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lda $2,9*64($16)
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wh64 ($1)
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wh64 ($2)
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lda $19,10*64($16)
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nop
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/* Main prefetching/write-hinting loop. */
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1: ldq $0,0($17)
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ldq $1,8($17)
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unop
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unop
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unop
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unop
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ldq $2,16($17)
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ldq $3,24($17)
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ldq $4,32($17)
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ldq $5,40($17)
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unop
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unop
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unop
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unop
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ldq $6,48($17)
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ldq $7,56($17)
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ldl $31,320($17)
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unop
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unop
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unop
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/* This gives the extra cycle of aeration above the minimum. */
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unop
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unop
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unop
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unop
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wh64 ($19)
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unop
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unop
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unop
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stq $0,0($16)
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subq $18,1,$18
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stq $1,8($16)
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unop
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unop
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stq $2,16($16)
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addq $17,64,$17
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stq $3,24($16)
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stq $4,32($16)
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stq $5,40($16)
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addq $19,64,$19
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unop
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stq $6,48($16)
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stq $7,56($16)
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addq $16,64,$16
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bne $18, 1b
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/* Prefetch the final 5 cache lines of the read stream. */
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lda $18,10
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ldl $31,320($17)
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ldl $31,384($17)
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ldl $31,448($17)
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ldl $31,512($17)
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ldl $31,576($17)
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nop
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nop
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/* Non-prefetching, non-write-hinting cleanup loop for the
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final 10 cache lines. */
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2: ldq $0,0($17)
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ldq $1,8($17)
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ldq $2,16($17)
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ldq $3,24($17)
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ldq $4,32($17)
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ldq $5,40($17)
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ldq $6,48($17)
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ldq $7,56($17)
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stq $0,0($16)
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subq $18,1,$18
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stq $1,8($16)
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addq $17,64,$17
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stq $2,16($16)
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stq $3,24($16)
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stq $4,32($16)
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stq $5,40($16)
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stq $6,48($16)
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stq $7,56($16)
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addq $16,64,$16
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bne $18, 2b
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ret
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nop
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unop
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nop
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.end copy_page
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