861fe90656
Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| boot | ||
| kernel | ||
| lib | ||
| math-emu | ||
| mm | ||
| oprofile | ||
| prom | ||
| solaris | ||
| defconfig | ||
| Kconfig | ||
| Kconfig.debug | ||
| Makefile | ||