33309ecda0
The dcache_by_line_op macro suffers from a couple of small problems:
First, the GAS directives that are currently being used rely on
assembler behavior that is not documented, and probably not guaranteed
to produce the correct behavior going forward. As a result, we end up
with some undefined symbols in cache.o:
$ nm arch/arm64/mm/cache.o
...
U civac
...
U cvac
U cvap
U cvau
This is due to the fact that the comparisons used to select the
operation type in the dcache_by_line_op macro are comparing symbols
not strings, and even though it seems that GAS is doing the right
thing here (undefined symbols by the same name are equal to each
other), it seems unwise to rely on this.
Second, when patching in a DC CVAP instruction on CPUs that support it,
the fallback path consists of a DC CVAU instruction which may be
affected by CPU errata that require ARM64_WORKAROUND_CLEAN_CACHE.
Solve these issues by unrolling the various maintenance routines and
using the conditional directives that are documented as operating on
strings. To avoid the complexity of nested alternatives, we move the
DC CVAP patching to __clean_dcache_area_pop, falling back to a branch
to __clean_dcache_area_poc if DCPOP is not supported by the CPU.
Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
258 lines
5.9 KiB
ArmAsm
258 lines
5.9 KiB
ArmAsm
/*
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* Cache maintenance
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/cpufeature.h>
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#include <asm/alternative.h>
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#include <asm/asm-uaccess.h>
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/*
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* flush_icache_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified region.
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* This is typically used when code has been written to a memory region,
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* and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(__flush_icache_range)
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/* FALLTHROUGH */
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/*
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* __flush_cache_user_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified region.
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* This is typically used when code has been written to a memory region,
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* and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(__flush_cache_user_range)
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uaccess_ttbr0_enable x2, x3, x4
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alternative_if ARM64_HAS_CACHE_IDC
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dsb ishst
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b 7f
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alternative_else_nop_endif
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dcache_line_size x2, x3
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sub x3, x2, #1
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bic x4, x0, x3
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1:
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user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE
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add x4, x4, x2
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cmp x4, x1
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b.lo 1b
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dsb ish
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7:
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alternative_if ARM64_HAS_CACHE_DIC
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isb
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b 8f
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alternative_else_nop_endif
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invalidate_icache_by_line x0, x1, x2, x3, 9f
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8: mov x0, #0
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1:
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uaccess_ttbr0_disable x1, x2
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ret
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9:
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mov x0, #-EFAULT
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b 1b
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ENDPROC(__flush_icache_range)
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ENDPROC(__flush_cache_user_range)
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/*
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* invalidate_icache_range(start,end)
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*
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* Ensure that the I cache is invalid within specified region.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(invalidate_icache_range)
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alternative_if ARM64_HAS_CACHE_DIC
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mov x0, xzr
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isb
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ret
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alternative_else_nop_endif
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uaccess_ttbr0_enable x2, x3, x4
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invalidate_icache_by_line x0, x1, x2, x3, 2f
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mov x0, xzr
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1:
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uaccess_ttbr0_disable x1, x2
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ret
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2:
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mov x0, #-EFAULT
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b 1b
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ENDPROC(invalidate_icache_range)
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/*
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* __flush_dcache_area(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned and invalidated to the PoC.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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ENTRY(__flush_dcache_area)
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dcache_by_line_op civac, sy, x0, x1, x2, x3
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ret
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ENDPIPROC(__flush_dcache_area)
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/*
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* __clean_dcache_area_pou(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned to the PoU.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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ENTRY(__clean_dcache_area_pou)
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alternative_if ARM64_HAS_CACHE_IDC
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dsb ishst
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ret
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alternative_else_nop_endif
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dcache_by_line_op cvau, ish, x0, x1, x2, x3
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ret
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ENDPROC(__clean_dcache_area_pou)
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/*
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* __inval_dcache_area(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are invalidated. Any partial lines at the ends of the interval are
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* also cleaned to PoC to prevent data loss.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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ENTRY(__inval_dcache_area)
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/* FALLTHROUGH */
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/*
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* __dma_inv_area(start, size)
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* - start - virtual start address of region
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* - size - size in question
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*/
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__dma_inv_area:
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add x1, x1, x0
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dcache_line_size x2, x3
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sub x3, x2, #1
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tst x1, x3 // end cache line aligned?
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bic x1, x1, x3
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b.eq 1f
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dc civac, x1 // clean & invalidate D / U line
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1: tst x0, x3 // start cache line aligned?
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bic x0, x0, x3
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b.eq 2f
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dc civac, x0 // clean & invalidate D / U line
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b 3f
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2: dc ivac, x0 // invalidate D / U line
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3: add x0, x0, x2
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cmp x0, x1
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b.lo 2b
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dsb sy
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ret
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ENDPIPROC(__inval_dcache_area)
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ENDPROC(__dma_inv_area)
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/*
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* __clean_dcache_area_poc(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned to the PoC.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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ENTRY(__clean_dcache_area_poc)
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/* FALLTHROUGH */
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/*
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* __dma_clean_area(start, size)
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* - start - virtual start address of region
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* - size - size in question
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*/
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__dma_clean_area:
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dcache_by_line_op cvac, sy, x0, x1, x2, x3
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ret
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ENDPIPROC(__clean_dcache_area_poc)
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ENDPROC(__dma_clean_area)
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/*
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* __clean_dcache_area_pop(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned to the PoP.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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ENTRY(__clean_dcache_area_pop)
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alternative_if_not ARM64_HAS_DCPOP
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b __clean_dcache_area_poc
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alternative_else_nop_endif
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dcache_by_line_op cvap, sy, x0, x1, x2, x3
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ret
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ENDPIPROC(__clean_dcache_area_pop)
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/*
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* __dma_flush_area(start, size)
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*
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* clean & invalidate D / U line
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*
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* - start - virtual start address of region
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* - size - size in question
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*/
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ENTRY(__dma_flush_area)
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dcache_by_line_op civac, sy, x0, x1, x2, x3
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ret
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ENDPIPROC(__dma_flush_area)
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/*
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* __dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(__dma_map_area)
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cmp w2, #DMA_FROM_DEVICE
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b.eq __dma_inv_area
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b __dma_clean_area
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ENDPIPROC(__dma_map_area)
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/*
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* __dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(__dma_unmap_area)
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cmp w2, #DMA_TO_DEVICE
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b.ne __dma_inv_area
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ret
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ENDPIPROC(__dma_unmap_area)
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