cbf27660e6
The OMAP4 L3 interconnect is split in 3 part for power saving reason. Because of that there is no l3_main like on OMAP2 & 3 but 3 differentes l3_main_X instances. In the case of OMAP4, query only the l3_main_1 part. The clock and voltage are shared across the 3 instances. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
148 lines
3.1 KiB
C
148 lines
3.1 KiB
C
/*
|
|
* pm.c - Common OMAP2+ power management-related code
|
|
*
|
|
* Copyright (C) 2010 Texas Instruments, Inc.
|
|
* Copyright (C) 2010 Nokia Corporation
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
#include <linux/io.h>
|
|
#include <linux/err.h>
|
|
|
|
#include <plat/omap-pm.h>
|
|
#include <plat/omap_device.h>
|
|
#include <plat/common.h>
|
|
|
|
#include <plat/powerdomain.h>
|
|
#include <plat/clockdomain.h>
|
|
|
|
static struct omap_device_pm_latency *pm_lats;
|
|
|
|
static struct device *mpu_dev;
|
|
static struct device *iva_dev;
|
|
static struct device *l3_dev;
|
|
static struct device *dsp_dev;
|
|
|
|
struct device *omap2_get_mpuss_device(void)
|
|
{
|
|
WARN_ON_ONCE(!mpu_dev);
|
|
return mpu_dev;
|
|
}
|
|
|
|
struct device *omap2_get_iva_device(void)
|
|
{
|
|
WARN_ON_ONCE(!iva_dev);
|
|
return iva_dev;
|
|
}
|
|
|
|
struct device *omap2_get_l3_device(void)
|
|
{
|
|
WARN_ON_ONCE(!l3_dev);
|
|
return l3_dev;
|
|
}
|
|
|
|
struct device *omap4_get_dsp_device(void)
|
|
{
|
|
WARN_ON_ONCE(!dsp_dev);
|
|
return dsp_dev;
|
|
}
|
|
EXPORT_SYMBOL(omap4_get_dsp_device);
|
|
|
|
/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
|
|
static int _init_omap_device(char *name, struct device **new_dev)
|
|
{
|
|
struct omap_hwmod *oh;
|
|
struct omap_device *od;
|
|
|
|
oh = omap_hwmod_lookup(name);
|
|
if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
|
|
__func__, name))
|
|
return -ENODEV;
|
|
|
|
od = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
|
|
if (WARN(IS_ERR(od), "%s: could not build omap_device for %s\n",
|
|
__func__, name))
|
|
return -ENODEV;
|
|
|
|
*new_dev = &od->pdev.dev;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Build omap_devices for processors and bus.
|
|
*/
|
|
static void omap2_init_processor_devices(void)
|
|
{
|
|
_init_omap_device("mpu", &mpu_dev);
|
|
_init_omap_device("iva", &iva_dev);
|
|
if (cpu_is_omap44xx()) {
|
|
_init_omap_device("l3_main_1", &l3_dev);
|
|
_init_omap_device("dsp", &dsp_dev);
|
|
} else {
|
|
_init_omap_device("l3_main", &l3_dev);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* This sets pwrdm state (other than mpu & core. Currently only ON &
|
|
* RET are supported. Function is assuming that clkdm doesn't have
|
|
* hw_sup mode enabled.
|
|
*/
|
|
int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
|
|
{
|
|
u32 cur_state;
|
|
int sleep_switch = 0;
|
|
int ret = 0;
|
|
|
|
if (pwrdm == NULL || IS_ERR(pwrdm))
|
|
return -EINVAL;
|
|
|
|
while (!(pwrdm->pwrsts & (1 << state))) {
|
|
if (state == PWRDM_POWER_OFF)
|
|
return ret;
|
|
state--;
|
|
}
|
|
|
|
cur_state = pwrdm_read_next_pwrst(pwrdm);
|
|
if (cur_state == state)
|
|
return ret;
|
|
|
|
if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
|
|
omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
|
|
sleep_switch = 1;
|
|
pwrdm_wait_transition(pwrdm);
|
|
}
|
|
|
|
ret = pwrdm_set_next_pwrst(pwrdm, state);
|
|
if (ret) {
|
|
printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
|
|
pwrdm->name);
|
|
goto err;
|
|
}
|
|
|
|
if (sleep_switch) {
|
|
omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
|
|
pwrdm_wait_transition(pwrdm);
|
|
pwrdm_state_switch(pwrdm);
|
|
}
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static int __init omap2_common_pm_init(void)
|
|
{
|
|
omap2_init_processor_devices();
|
|
omap_pm_if_init();
|
|
|
|
return 0;
|
|
}
|
|
device_initcall(omap2_common_pm_init);
|
|
|